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/Zephyr-Core-3.6.0/dts/bindings/gpio/
Dti,boosterpack-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
15 through 40. The BoosterPack pinout is depicted below:
17 1 3.3V 21 5V 40 GPIO 20 GND
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
Draspberrypi-40pins-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on Raspberry Pi 40-pin header.
11 - 3V3 5V -
12 0 GPIO2/I2C1_SDA 5V -
13 1 GPIO3/I2C1_SCL GND -
15 - GND GPIO15/UART0_RXD 4
17 7 GPIO27 GND -
19 - 3V3 GPIO24 10
20 11 GPIO10/SPI0_MOSI GND -
23 - GND GPIO7/SPI0_CE1 16
[all …]
Drichtek,rt1718s.yaml2 # SPDX-License-Identifier: Apache-2.0
9 address. Feature-specific(GPIO, TCPC) properties should be placed in a child
14 rt1718s_port0: rt1718s@40 {
17 irq-gpios = <&gpioe 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
20 compatible = "richtek,rt1718s-gpio-port";
22 gpio-controller;
23 #gpio-cells = <2>;
31 include: [i2c-device.yaml]
34 irq-gpios:
35 type: phandle-array
[all …]
/Zephyr-Core-3.6.0/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "40-ohm";
16 slew-rate = "slow";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1
28 drive-open-drain: ODE=1
29 slew-rate: SRE=<enum_idx>
30 drive-strength: DSE=<enum_idx>
31 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
33 If only required properties are supplied, the pin will have the following
[all …]
/Zephyr-Core-3.6.0/tests/drivers/gpio/gpio_basic_api/boards/
Dup_squared.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * This uses pin 40 on HAT as LED, and pin 38 as interrupt line.
12 * () Advanced -> HAT Configurations:
13 * - HD-Audio / I2S6 Selec -> Disabled
15 * - GPIO 27 (Pin38) Confi -> Input
16 * - GPIO 28 (Pin40) Confi -> Output
21 compatible = "test-gpio-basic-api";
23 out-gpios = <&gpio_w 19 0>; /* HAT Pin 40 */
24 in-gpios = <&gpio_w 18 0>; /* HAT Pin 38 */
/Zephyr-Core-3.6.0/tests/drivers/gpio/gpio_api_1pin/boards/
Dup_squared.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * This uses pin 40 on HAT as LED.
12 * () Advanced -> HAT Configurations:
13 * - HD-Audio / I2S6 Selec -> Disabled
15 * - GPIO 28 (Pin40) Confi -> Output
24 compatible = "gpio-leds";
27 label = "HAT Pin 40 as LED";
/Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/common/
DKconfig.soc2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
93 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
94 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
112 bool "40MHz clock speed"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
[all …]
/Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
237 #define MIO_GROUP_CAN1_8_GRP_PINS 40, 41
260 #define MIO_GROUP_UART1_8_GRP_PINS 40, 41
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra-common.h4 * SPDX-License-Identifier: Apache-2.0
25 #define RA_PINCFG(port, pin, psel, opt) \ argument
26 ((((psel)&PSEL_MASK) << PSEL_POS) | (((pin)&PIN_MASK) << PIN_POS) | \
30 #if RA_SOC_PINS >= 40
31 #define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
35 #define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
39 #define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
43 #define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
/Zephyr-Core-3.6.0/samples/boards/up_squared/gpio_counter/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
22 * as a 4-bit value (bin 0, 1, 2, 3 -> HAT Pin 35, 37, 38, 40).
23 * The counter increments for each change from 0 to 1 on HAT Pin 16.
27 * () Advanced -> HAT Configurations:
28 * - HD-Audio / I2S6 Selec -> Disabled
29 * - GPIO / PWM3 Selection -> GPIO
30 * - GPIO / I2S2 Selection -> GPIO
32 * - GPIO 19 (Pin16) Confi -> Input
34 * - GPIO 14 (Pin35) Confi -> Output
35 * - GPIO 15 (Pin37) Confi -> Output
[all …]
/Zephyr-Core-3.6.0/dts/bindings/sensor/
Dvishay,vcnl4040.yaml2 # SPDX-License-Identifier: Apache-2.0
10 include: [sensor-device.yaml, i2c-device.yaml]
13 int-gpios:
14 type: phandle-array
16 The INT pin signals that a programmable interrupt function
18 triggered. The sensor generates an active-low level signal
21 led-current:
27 - 50
28 - 75
29 - 100
[all …]
/Zephyr-Core-3.6.0/samples/boards/up_squared/gpio_counter/
DREADME.rst11 The sample enables a pin as GPIO input (active high) that triggers the increment
13 each change from 0 to 1 on HAT Pin 16 (BIOS Pin 19). The value of the counter is
14 represented on GPIO output (active high) as a 4-bit value
15 (bin 0, 1, 2, 3 -> HAT Pin 35, 37, 38, 40).
17 +------------+-----------------------------+
21 +------------+-----+-----+-----+-----+-----+
22 | HAT Pin | 16 | 40 | 39 | 37 | 35 |
23 +------------+-----+-----+-----+-----+-----+
24 | BIOS Pin | 19 | 38 | 27 | 15 | 14 |
25 +------------+-----+-----+-----+-----+-----+
[all …]
/Zephyr-Core-3.6.0/drivers/pinctrl/
Dpinctrl_ti_cc32xx.c3 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
15 /* pin to pad mapping (255 indicates invalid pin) */
18 21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
26 uint8_t pin; in pinctrl_configure_pin() local
28 pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK; in pinctrl_configure_pin()
29 if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) { in pinctrl_configure_pin()
30 return -EINVAL; in pinctrl_configure_pin()
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/
Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 /** Definitions of pin functions */
51 #define SMARTBOND_FUNC_PORT3_DCF 40
76 #define SMARTBOND_PINMUX(func, port, pin) \ argument
79 (pin) << SMARTBOND_PINMUX_PIN_POS)
/Zephyr-Core-3.6.0/dts/bindings/can/
Dmicrochip,mcp251xfd.yaml2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
22 bus-speed = <125000>;
23 sample-point = <875>;
24 bus-speed-data = <1000000>;
25 sample-point-data = <875>;
31 include: [spi-device.yaml, can-fd-controller.yaml]
[all …]
/Zephyr-Core-3.6.0/boards/shields/g1120b0mipi/doc/
Dindex.rst10 1-lane MIPI interface. This display connects to the i.MX RT595 Evaluation Kit.
16 This display uses a 40 pin FPC interface, which is available on many
22 +-----------------------+------------------------+
23 | FPC Connector Pin | Function |
26 +-----------------------+------------------------+
28 +-----------------------+------------------------+
30 +-----------------------+------------------------+
32 +-----------------------+------------------------+
34 +-----------------------+------------------------+
36 +-----------------------+------------------------+
[all …]
/Zephyr-Core-3.6.0/boards/shields/rk055hdmipi4ma0/doc/
Dindex.rst16 This display uses a 40 pin FPC interface, which is available on many
22 +-----------------------+------------------------+
23 | FPC Connector Pin | Function |
26 +-----------------------+------------------------+
28 +-----------------------+------------------------+
30 +-----------------------+------------------------+
32 +-----------------------+------------------------+
34 +-----------------------+------------------------+
36 +-----------------------+------------------------+
38 +-----------------------+------------------------+
[all …]
/Zephyr-Core-3.6.0/boards/shields/rk055hdmipi4m/doc/
Dindex.rst16 This display uses a 40 pin FPC interface, which is available on many
22 +-----------------------+------------------------+
23 | FPC Connector Pin | Function |
26 +-----------------------+------------------------+
28 +-----------------------+------------------------+
30 +-----------------------+------------------------+
32 +-----------------------+------------------------+
34 +-----------------------+------------------------+
36 +-----------------------+------------------------+
38 +-----------------------+------------------------+
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/adt7420/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
12 Enable the driver for Analog Devices ADT7420 High-Accuracy
13 16-bit Digital I2C Temperature Sensors.
27 range -40 150
30 The critical overtemperature pin asserts when the temperature
/Zephyr-Core-3.6.0/samples/subsys/display/lvgl/boards/
Dnative_posix.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
8 #include <zephyr/dt-bindings/lvgl/lvgl.h>
16 compatible = "gpio-qdec";
18 steps-per-period = <4>;
20 sample-time-us = <2000>;
21 idle-timeout-ms = <200>;
25 compatible = "gpio-keys";
27 /* gpio0 pin 0 is already aliased to led0 */
59 compatible = "zephyr,lvgl-button-input";
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f3/
Dstm32f302Xc.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 reg = <0x20000000 DT_SIZE_K(40)>;
16 flash-controller@40022000 {
23 compatible = "st,stm32-dma-v2bis";
24 #dma-cells = <2>;
32 compatible = "st,stm32-uart";
39 pinctrl: pin-controller@48000000 {
41 compatible = "st,stm32-gpio";
42 gpio-controller;
43 #gpio-cells = <2>;
[all …]
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt53v_db_40_nrf5340/
DKconfig1 # Ratac MDBT53V-DB-40 nRF5340 board configuration
3 # Copyright (c) 2019 - 2021 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
32 Note: GPIO pin allocation can only be configured by the secure Application
33 MCU firmware, so when this option is used with the non-secure version of
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt53_db_40_nrf5340/
DKconfig1 # Ratac MDBT53-DB-40 nRF5340 board configuration
3 # Copyright (c) 2019 - 2021 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
32 Note: GPIO pin allocation can only be configured by the secure Application
33 MCU firmware, so when this option is used with the non-secure version of
/Zephyr-Core-3.6.0/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c5 * SPDX-License-Identifier: Apache-2.0
36 gpio_pin_set(dev, DIO9_PIN, (byte >> (7 - i)) & 0x01); in CC1352R1_LAUNCHXL_sendExtFlashByte()
51 * Keep CS high at least 40 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
87 printk("%s: device not ready.\n", dev->name); in CC1352R1_LAUNCHXL_shutDownExtFlash()
91 /* Set SPI Flash CS pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
93 /* Set SPI Flash CLK pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
95 /* Set SPI Flash MOSI pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
97 /* Set SPI Flash MISO pin as input */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/
Dindex.rst3 Raytac MDBT53V-DB-40
9 Raytac MDBT53V-DB-40 demo board is a development board based on the Raytac MDBT53V-1M module,
10 using Nordic Semiconductor nRF5340 ARM Cortex-M33 SoC. Its design concept is to connect all
11 of the module's pins to 2.54mm pin headers. It is convenient for developers to verify whether
14 The nRF5340 inside the MDBT53V-1M module is a
15 dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
17 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
18 Armv8-M Security Extension, running at up to 128 MHz, referred to as
20 * a secondary Arm Cortex-M33 core, with a reduced feature set, running
34 * :abbr:`I2C (Inter-Integrated Circuit)`
[all …]

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