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/Zephyr-Core-3.7.0/dts/bindings/flash_controller/
Dst,stm32-ospi-nor.yaml47 - OSPI_QUAD_MODE <4> = Quad mode on 4 data lines
52 - 4
71 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
72 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
79 supporting 1-4-4 mode also would support fast page programming.
88 * OSPI_QUAD_MODE -> PP 1-4-4 (0x38)
93 4 byte addressing mode.
96 4 byte opcodes.
98 * PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12)
99 * PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34)
[all …]
/Zephyr-Core-3.7.0/soc/espressif/esp32/
Dgdbstub.c22 .alignment = 4,
29 .alignment = 4,
36 .alignment = 4,
43 .alignment = 4,
50 .alignment = 4,
57 .alignment = 4,
64 .alignment = 4,
71 .alignment = 4,
78 .alignment = 4,
88 .alignment = 4,
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/Zephyr-Core-3.7.0/modules/hal_nordic/
DKconfig14 prompt "Source of the IEEE 802.15.4 radio driver"
22 bool "NRF IEEE 802.15.4 radio driver"
28 This option enables nRF IEEE 802.15.4 radio driver in Zephyr. Note,
32 file. As the nRF IEEE 802.15.4 radio driver defines IRQ configuration
47 prompt "nRF IEEE 802.15.4 Service Layer Type"
57 bool "nRF 802.15.4 temperature update"
60 Enable temperature update for nRF 802.15.4 driver
63 int "nRF52 IEEE 802.15.4 temperature update initialization priority"
67 Set the initialization priority of a temperature update for nRF 802.15.4 driver.
70 int "nRF 802.15.4 temperature update period in milliseconds"
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/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a779f0.h17 #define PIN_HCTS0_N RCAR_GP_PIN(0, 4)
38 #define PIN_GP1_04 RCAR_GP_PIN(1, 4)
63 #define PIN_QSPI1_IO3 RCAR_GP_PIN(2, 4)
80 #define PIN_TSN0_MDC RCAR_GP_PIN(3, 4)
95 #define PIN_GP4_00 RCAR_GP_PIN(4, 0)
96 #define PIN_GP4_01 RCAR_GP_PIN(4, 1)
97 #define PIN_GP4_02 RCAR_GP_PIN(4, 2)
98 #define PIN_GP4_03 RCAR_GP_PIN(4, 3)
99 #define PIN_GP4_04 RCAR_GP_PIN(4, 4)
100 #define PIN_GP4_05 RCAR_GP_PIN(4, 5)
[all …]
Dpinctrl-r8a77951.h17 #define PIN_D4 RCAR_GP_PIN(0, 4)
33 #define PIN_A4 RCAR_GP_PIN(1, 4)
62 #define PIN_IRQ4 RCAR_GP_PIN(2, 4)
77 #define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4)
89 #define PIN_SD2_CLK RCAR_GP_PIN(4, 0)
90 #define PIN_SD2_CMD RCAR_GP_PIN(4, 1)
91 #define PIN_SD2_DATA0 RCAR_GP_PIN(4, 2)
92 #define PIN_SD2_DATA1 RCAR_GP_PIN(4, 3)
93 #define PIN_SD2_DATA2 RCAR_GP_PIN(4, 4)
94 #define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5)
[all …]
Dpinctrl-r8a77961.h18 #define PIN_D4 RCAR_GP_PIN(0, 4)
34 #define PIN_A4 RCAR_GP_PIN(1, 4)
63 #define PIN_IRQ4 RCAR_GP_PIN(2, 4)
78 #define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4)
90 #define PIN_SD2_CLK RCAR_GP_PIN(4, 0)
91 #define PIN_SD2_CMD RCAR_GP_PIN(4, 1)
92 #define PIN_SD2_DATA0 RCAR_GP_PIN(4, 2)
93 #define PIN_SD2_DATA1 RCAR_GP_PIN(4, 3)
94 #define PIN_SD2_DATA2 RCAR_GP_PIN(4, 4)
95 #define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5)
[all …]
Dpinctrl-r7fa4m1xxxxxx.h22 #define P004_AMP2O RA_PINCFG__64(0, 4, 0x02, RA_PINCFG_FUNC | RA_PINCFG_ANALOG)
23 #define P004_AN004 RA_PINCFG__64(0, 4, 0x01, RA_PINCFG_ANALOG)
97 #define P104_COM0 RA_PINCFG__48(1, 4, 0x0D, RA_PINCFG_FUNC)
98 #define P104_GTETRGB RA_PINCFG__48(1, 4, 0x02, RA_PINCFG_FUNC)
99 #define P104_GTIOC1B RA_PINCFG__48(1, 4, 0x03, RA_PINCFG_FUNC)
100 #define P104_KR04 RA_PINCFG__48(1, 4, 0x08, RA_PINCFG_FUNC)
101 #define P104_MISO0 RA_PINCFG__48(1, 4, 0x04, RA_PINCFG_FUNC)
102 #define P104_RXD0 RA_PINCFG__48(1, 4, 0x04, RA_PINCFG_FUNC)
103 #define P104_SCL0 RA_PINCFG__48(1, 4, 0x04, RA_PINCFG_FUNC)
104 #define P104_SSLA1 RA_PINCFG__48(1, 4, 0x06, RA_PINCFG_FUNC)
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/Zephyr-Core-3.7.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
48 '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6',
51 '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4',
52 '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6',
55 '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
59 '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5',
63 '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5', '5', '5',
67 '3', '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5',
71 '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6',
[all …]
/Zephyr-Core-3.7.0/doc/connectivity/networking/api/
Dieee802154.rst3 IEEE 802.15.4
13 IEEE 802.15.4 is a technical standard which defines the operation of low-rate
15 standard, see the `IEEE 802.15.4 Wikipedia article
23 We're currently following the IEEE 802.15.4-2020 specification. This version is
24 backwards compatible with IEEE 802.15.4-2015, parts of which are contained in
26 were accepted into the standard, namely IEEE 802.15.4g (SUN FSK) and IEEE
27 802.15.4e (TSCH) which are of relevance to industrial IoT and automation. For
28 recent developments in UWB ranging technology, see IEEE 802.15.4z which is not
32 to IEEE 802.15.4-2020 section, table and figure numbering - unless otherwise
35 Zephyr supports both, native IEEE 802.15.4 and Thread, with 6LoWPAN. Zephyr's
[all …]
/Zephyr-Core-3.7.0/tests/bsim/bluetooth/host/iso/bis/
Dprj.conf12 CONFIG_BT_ISO_TX_BUF_COUNT=4
13 CONFIG_BT_ISO_MAX_CHAN=4
21 CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=4
23 CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=4
25 CONFIG_BT_CTLR_ISO_TX_BUFFERS=4
26 CONFIG_BT_CTLR_ISOAL_SOURCES=4
27 CONFIG_BT_CTLR_ISOAL_SINKS=4
/Zephyr-Core-3.7.0/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h20 * 4
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
30 #define CHAR_5 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
31 #define CHAR_6 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
33 #define CHAR_8 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
34 #define CHAR_9 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
37 #define CHAR_C (BIT(0) | BIT(1) | BIT(3) | BIT(4))
38 #define CHAR_E (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
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/Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi43 wui_io94: wui0-2-4 {
44 miwus = <&miwu0 1 4>; /* GPIO94 */
69 wui_ioa2: wui0-3-4 {
70 miwus = <&miwu0 2 4>; /* GPIOA2 */
83 wui_ioa6: wui0-4-0 {
86 wui_ioa7: wui0-4-1 {
89 wui_iob0: wui0-4-2 {
92 wui_smb0_2: wui0-4-3 {
95 wui_smb1_3: wui0-4-4 {
96 miwus = <&miwu0 3 4>; /* SMB1/3 */
[all …]
/Zephyr-Core-3.7.0/boards/native/doc/
Dlayering.svg34 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
38 <g id="shape2-4" v:mID="2" v:groupContext="shape" transform="translate(98.3352,-46.6765)">
41 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
48 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
52 <g id="shape4-10" v:mID="4" v:groupContext="shape" transform="translate(10.4612,-92.0309)">
53 <title>Sheet.4</title>
55 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
63 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
72 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
79 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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DPort_vs_QEMU_vs.svg61 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
65 <g id="shape4-15" v:mID="4" v:groupContext="shape" transform="translate(-3.18898,-199.134)">
66 <title>Sheet.4</title>
68 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
81 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
89 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
97 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
109 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
116 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
123 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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DZephyr_and_bsim.svg25 …11 {stroke:#000000;stroke-dasharray:0,20;stroke-linecap:round;stroke-linejoin:round;stroke-width:4}
34 …<marker id="mrkr4-51" class="st10" v:arrowType="4" v:arrowSize="1" v:setback="2.648" refX="2.648" …
38 …<marker id="mrkr4-53" class="st10" v:arrowType="4" v:arrowSize="1" v:setback="2.72" refX="-2.72" o…
43 <g v:mID="4" v:index="4" v:groupContext="foregroundPage">
51 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
54 …<text x="4" y="299.52" class="st2" v:langID="6153"><v:paragraph/><v:tabList/>HW models<v:tabChar/>…
55 <g id="shape2-4" v:mID="2" v:groupContext="shape" transform="translate(107.866,-117.809)">
58 <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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70 <g id="shape4-11" v:mID="4" v:groupContext="shape" transform="translate(8.65313,-154.66)">
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/Zephyr-Core-3.7.0/subsys/net/l2/ieee802154/
DKconfig5 bool "IEEE 802.15.4 Radio"
8 Add support for low rate WPAN IEEE 802.15.4 technology.
19 module-str = Log level for IEEE 802.15.4
20 module-help = Enables IEEE 802.15.4 code to output debug messages.
24 bool "IEEE 802.15.4 packet display"
27 Enable printing out in/out 802.15.4 packets. This is extremely
57 the device might expose more or less 802.15.4 protocol features.
71 bool "IEEE 802.15.4 shell module"
79 bool "802.15.4 fragmentation support"
83 If IPv6 packets size more than 802.15.4 MTU, packet is fragmented
[all …]
/Zephyr-Core-3.7.0/drivers/flash/
Dspi_nor.h29 #define SPI_NOR_CMD_QREAD 0x6B /* Read data (1-1-4) */
30 #define SPI_NOR_CMD_4READ 0xEB /* Read data (1-4-4) */
35 #define SPI_NOR_CMD_PP_1_1_4 0x32 /* Quad Page program (1-1-4) */
36 #define SPI_NOR_CMD_PP_1_4_4 0x38 /* Quad Page program (1-4-4) */
39 #define SPI_NOR_CMD_SE_4B 0x21 /* Sector erase 4 byte address*/
45 #define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */
53 #define SPI_NOR_CMD_READ_4B 0x13 /* Read data 4 Byte Address */
54 #define SPI_NOR_CMD_READ_FAST_4B 0x0C /* Fast Read 4 Byte Address */
55 #define SPI_NOR_CMD_DREAD_4B 0x3C /* Read data (1-1-2) 4 Byte Address */
56 #define SPI_NOR_CMD_2READ_4B 0xBC /* Read data (1-2-2) 4 Byte Address */
[all …]
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/reset/
Dnumaker_m2l31x_reset.h29 #define SYS_IPRST0_USBHRST_Pos 4
37 #define SYS_IPRST1_TMR2RST_Pos 4
94 #define NUMAKER_GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos)
95 #define NUMAKER_TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos)
96 #define NUMAKER_TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos)
97 #define NUMAKER_TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos)
98 #define NUMAKER_TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos)
99 #define NUMAKER_ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos)
100 #define NUMAKER_I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos)
101 #define NUMAKER_I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos)
[all …]
/Zephyr-Core-3.7.0/tests/drivers/counter/counter_basic_api/boards/
Dnrf54h20dk_nrf54h20_common.dtsi15 prescaler = <4>;
20 prescaler = <4>;
25 prescaler = <4>;
30 prescaler = <4>;
35 prescaler = <4>;
40 prescaler = <4>;
45 prescaler = <4>;
50 prescaler = <4>;
Dnrf54l15pdk_nrf54l15_cpuapp.overlay7 prescaler = <4>;
12 prescaler = <4>;
17 prescaler = <4>;
22 prescaler = <4>;
27 prescaler = <4>;
32 prescaler = <4>;
/Zephyr-Core-3.7.0/include/zephyr/drivers/usb_c/
Dusbc_tc.h32 * See Table 4-3 VBUS Sink Characteristics
38 * See Table 4-3 VBUS Sink Characteristics
45 * See Table 4-29 VBUS and VCONN Timing Parameters
52 * See Table 4-29 VBUS and VCONN Timing Parameters
58 * See Table 4-29 VBUS and VCONN Timing Parameters
64 * until the Sink sources minimum VCONN voltage (see Table 4-5)
65 * See Table 4-29 VBUS and VCONN Timing Parameters
72 * See Table 4-29 VBUS and VCONN Timing Parameters
79 * See Table 4-29 VBUS and VCONN Timing Parameters
85 * See Table 4-30 DRP Timing Parameters
[all …]
/Zephyr-Core-3.7.0/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h45 BIT(5) | BIT(4) | \
62 #define LSM6DSL_MASK_FIFO_CTRL3_DEC_FIFO_GYRO (BIT(5) | BIT(4) | \
74 #define LSM6DSL_MASK_FIFO_CTRL4_DEC_DS4_FIFO (BIT(5) | BIT(4) | \
83 BIT(4) | BIT(3))
102 #define LSM6DSL_MASK_INT1_CTRL_FIFO_OVR BIT(4)
103 #define LSM6DSL_SHIFT_INT1_CTRL_FIFO_OVR 4
120 #define LSM6DSL_MASK_INT2_CTRL_FIFO_OVR BIT(4)
121 #define LSM6DSL_SHIFT_INT2_CTRL_FIFO_OVR 4
136 BIT(5) | BIT(4))
137 #define LSM6DSL_SHIFT_CTRL1_XL_ODR_XL 4
[all …]
/Zephyr-Core-3.7.0/dts/arm/infineon/cat3/xmc/
Dxmc4500_F100x1024-intc.dtsi13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
19 XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */
25 XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */
27 XMC4XXX_INTC_SET_LINE_MAP(1, 4, 4, 2) /* ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 */
33 XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */
35 XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
36 XMC4XXX_INTC_SET_LINE_MAP(2, 1, 4, 4) /* ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 */
38 XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */
40 XMC4XXX_INTC_SET_LINE_MAP(1, 2, 4, 6) /* ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 */
[all …]
/Zephyr-Core-3.7.0/drivers/ieee802154/
Dieee802154_rf2xx_regs.h23 #define RX2XX_FRAME_TRAC_INDEX 4
108 #define RF2XX_PAD_IO_CLKM 4
109 #define RF2XX_PMU_EN 4
110 #define RF2XX_PMU_IF_INVERSE 4
118 #define RF2XX_RX_BL_CTRL 4
127 #define RF2XX_PA_SHR_LT 4
142 #define RF2XX_CCA_CS_THRES 4
154 #define RF2XX_OQPSK_SUB1_RC_EN 4
155 #define RF2XX_ALT_SPECTRUM 4
176 #define RF2XX_CCA_ED_DONE 4
[all …]
/Zephyr-Core-3.7.0/tests/subsys/dsp/print_format/src/
Dmain.c33 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 0)); in ZTEST()
36 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 1)); in ZTEST()
39 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, -2)); in ZTEST()
57 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 0)); in ZTEST()
60 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 1)); in ZTEST()
63 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, -2)); in ZTEST()
120 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 0)); in ZTEST()
123 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 1)); in ZTEST()
126 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, -2)); in ZTEST()
144 snprintf(buffer, 256, "%" PRIq(4), PRIq_arg(q, 4, 0)); in ZTEST()
[all …]

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