D | ibecc.h | 64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */ 81 /* Capability register, offset 0xec, 32 bit */ 94 * ERRSTS_REG with 32 bit access and get this 16 bits 142 /* Memory channel decoding register, 32 bit */ 144 #define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0) argument 146 #define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3) argument 148 #define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4) argument 150 #define INTER_CHAN_CH_S_SIZE BITFIELD(v, 19, 12) 152 /* DRAM decode stage 2 registers, 32 bit */ 155 #define DIMM_L_MAP(v) BITFIELD(v, 0, 0) argument [all …]
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