64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */
81 /* Capability register, offset 0xec, 32 bit */
94  * ERRSTS_REG with 32 bit access and get this 16 bits
142 /* Memory channel decoding register, 32 bit */
144 #define INTER_CHAN_DDR_TYPE(v)	BITFIELD(v, 2, 0)  argument
146 #define INTER_CHAN_ECHM(v)	BITFIELD(v, 3, 3)  argument
148 #define INTER_CHAN_CH_L_MAP(v)	BITFIELD(v, 4, 4)  argument
150 #define INTER_CHAN_CH_S_SIZE	BITFIELD(v, 19, 12)
152 /* DRAM decode stage 2 registers, 32 bit */
155 #define DIMM_L_MAP(v)		BITFIELD(v, 0, 0)  argument
157 /* DIMM channel characteristic 2 registers, 32 bit */
160 #define DIMM_L_SIZE(v)		(BITFIELD(v, 6, 0) << 29)  argument
162 #define DIMM_L_WIDTH(v)		BITFIELD(v, 8, 7)  argument
164 #define DIMM_S_SIZE(v)		(BITFIELD(v, 22, 16) << 29)  argument
166 #define DIMM_S_WIDTH(v)		BITFIELD(v, 25, 24)  argument
169 /* MC Channel Selection register, 32 bit */
172 /* MC Enhanced Channel Selection register, 32 bit */