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/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
36 3 - XTAL_32KHZ : 32768Hz from the crystal oscillator.
37 4 - XTAL_16KHZ : 16384Hz from the crystal oscillator.
38 5 - XTAL_1KHZ : 1024Hz from the crystal oscillator.
Dst,stm32-lptim.yaml35 For example, when LPTIM is clocked by the LSE (32768Hz) and st,prescaler = <32>:
/Zephyr-latest/drivers/timer/
DKconfig.gecko22 cycles, that is ~183 us @ 32768 Hz (LFXO, LFRCO) or
23 ~6 ms @ 1000 Hz (ULFRCO).
29 ~31 us @ 32768 Hz or ~1 ms @ 1000 Hz. This reduces timing
Dite_it8xxx2_timer.c21 BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
22 "ITE RTOS timer HW frequency is fixed at 32768Hz");
28 /* Event timer max count is 512 sec (base on clock source 32768Hz) */
61 #define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000) argument
141 hw_cnt = MS_TO_COUNT(32768, 5/*ms*/); in timer_5ms_one_shot()
338 hw_cnt = MS_TO_COUNT(32768, ms); in timer_init()
Dmchp_mec5_ktimer.c22 BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
23 "MCHP MEC5 ktimer HW frequency is fixed at 32768");
41 * frequency of 32768 Hz. The driver is based upon the Intel local APIC
47 * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=<hz> must be set to 32768.
53 * CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
Dmchp_xec_rtos_timer.c19 BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
20 "XEC RTOS timer HW frequency is fixed at 32768");
38 * frequency of 32768 Hz. The driver is based upon the Intel local APIC
44 * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=<hz> must be set to 32768.
50 * CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/
DKconfig.defconfig11 # XEC RTOS timer HW frequency is fixed at 32768 Hz.
12 # The driver requires tickless mode and ticks per second to be 32768 for
16 default 32768
19 default 32768
/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/
DKconfig.defconfig11 # XEC RTOS timer HW frequency is fixed at 32768 Hz.
12 # The driver requires tickless mode and ticks per second to be 32768 for
16 default 32768
19 default 32768
/Zephyr-latest/dts/bindings/rtc/
Dnxp,pcf8523.yaml29 default: 32768
31 - 32768
40 Frequency of the CLKOUT signal in Hertz (Hz). Default is 32768 Hz which corresponds to the
Dmotorola,mc146818.yaml14 default: 32768
18 - 32768
19 description: Frequency of the input-clock in Hertz (Hz)
Dmicrocrystal,rv3028.yaml16 - 32768
23 Frequency of the CLKOUT signal in Hertz (Hz). If omitted, the CLKOUT pin is LOW.
/Zephyr-latest/dts/bindings/clock/
Dsilabs,series2-lfxo.yaml21 enum: [2, 256, 1024, 2048, 4096, 8192, 16384, 32768]
25 Mode of operation. Defaults to "xtal", expecting a 32768 Hz crystal oscillator on XI and XO
/Zephyr-latest/boards/intel/ish/
DKconfig.defconfig12 default 2048 if HPET_TIMER # HPET timer's frequency is 32768 HZ
/Zephyr-latest/drivers/led/
Dled_mchp_xec.c70 /* Blink mode source frequency is 32768 Hz */
71 #define XEC_BBLED_BLINK_CLK_SRC_HZ 32768u
72 /* Fblink = 32768 / (256 * (prescaler+1))
74 * Maximum Fblink = 128 Hz or 7.8125 ms
97 * (prescale+1) = (32768 * Tblink_ms) / (256 * 1000)
132 * The counter uses the 32768 Hz clock and is pre-scaled by the delay
133 * counter. Maximum blink rate is 128Hz to 32.25 mHz (7.8 ms to 32 seconds).
135 * Fblink = 32768 / ((prescale + 1) * 256)
/Zephyr-latest/soc/espressif/
DKconfig53 - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
54 - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
/Zephyr-latest/drivers/ieee802154/
DKconfig.mcr20a51 bool "62500 Hz"
54 bool "32768 Hz"
/Zephyr-latest/samples/boards/espressif/xt_wdt/
DREADME.rst10 To properly run this sample, you need to have a board with an external 32.728 Hz
57 [00:00:01.287,000] <inf> xt_wdt_sample: Current RTC SLOW clock rate: 32768 Hz
60 [00:00:03.554,000] <inf> xt_wdt_sample: Current RTC SLOW clock rate: 136000 Hz
/Zephyr-latest/samples/boards/st/power_mgmt/blinky/
DREADME.rst15 For example, when clocking the low power Timer with LSE clock at 32768Hz and adding a
16 prescaler of <32>, then the kernel sleep period can reach 65536 * 32/32768 = 64 seconds
/Zephyr-latest/dts/bindings/spi/
Dspi-device.yaml16 description: Maximum clock frequency of device's SPI interface in Hz
39 32768 SPI_FRAME_FORMAT_TI
42 - 32768
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/lll/
Dlll_vendor.h19 * and ticker_update. Set to 32 us, which is ~1 tick with 32768 Hz
/Zephyr-latest/tests/kernel/timer/starve/
DREADME.txt20 For example a system that uses a 32768-Hz internal timer counter with
/Zephyr-latest/drivers/rtc/
Drtc_ifx_cat1.c74 * cycles at 32768 Hz.
76 * ROUND_DOWN(ppb * 32768Hz * 60min * 60sec / 1000000000, 128) / 128
83 * 32768 Hz to parts per billion
85 * wps * 128 * 1000000000 / 32768Hz * 60min * 60sec
/Zephyr-latest/soc/mediatek/mt8xxx/
DKconfig.defconfig46 default $(dt_node_int_prop_int,$(dt_nodelabel_path,ostimer64),freq-hz)
56 default 32768
/Zephyr-latest/dts/bindings/pwm/
Dnordic,nrf-sw-pwm.yaml20 RTC: needs to be set to 0, which gives 32768 Hz base clock for PWM
/Zephyr-latest/drivers/watchdog/
Dwdt_npcx.c51 * by npcx watchdog is 256 * (32 * 32768) / 32768 = 8192 sec.
52 * The maximum time supported of T0OUT is 65536 * 32 / 32768 = 64 sec.
59 * clocks since touching WD timer. 3 / (32768 / 1024) HZ = 93.75ms
190 * supported by it is 256 * (32 * 32) / 32768 = 8 sec. This makes the in wdt_npcx_install_timeout()
363 * - T0 Timer freq is LFCLK/32 Hz in wdt_npcx_init()
364 * - Watchdog freq is T0CLK/32 Hz (ie. LFCLK/1024 Hz) in wdt_npcx_init()

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