Home
last modified time | relevance | path

Searched full:31 (Results 1 – 25 of 859) sorted by relevance

12345678910>>...35

/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q7.c50 DEFINE_CORRELATE_TEST(30, 31);
55 DEFINE_CORRELATE_TEST(31, 31);
56 DEFINE_CORRELATE_TEST(31, 32);
57 DEFINE_CORRELATE_TEST(31, 33);
58 DEFINE_CORRELATE_TEST(31, 34);
59 DEFINE_CORRELATE_TEST(31, 49);
60 DEFINE_CORRELATE_TEST(32, 31);
65 DEFINE_CORRELATE_TEST(33, 31);
70 DEFINE_CORRELATE_TEST(48, 31);
107 DEFINE_CONV_TEST(30, 31);
[all …]
/Zephyr-Core-3.5.0/tests/unit/pot/
Dlog2.c25 zassert_equal(31, LOG2(BIT(31))); in ZTEST()
26 zassert_equal(31, LOG2(BIT(31) + 1)); in ZTEST()
27 zassert_equal(31, LOG2(UINT32_MAX)); in ZTEST()
Dlog2.cpp26 zassert_equal(31, LOG2(BIT(31))); in ZTEST()
27 zassert_equal(31, LOG2(BIT(31) + 1)); in ZTEST()
28 zassert_equal(31, LOG2(UINT32_MAX)); in ZTEST()
Dlog2ceil.c25 zassert_equal(31, LOG2CEIL(BIT(31))); in ZTEST()
26 zassert_equal(32, LOG2CEIL(BIT(31) + 1)); in ZTEST()
Dlog2ceil.cpp30 zassert_equal(31, LOG2CEIL(BIT(31))); in ZTEST()
31 zassert_equal(32, LOG2CEIL(BIT(31) + 1)); in ZTEST()
Dnhpot.c27 zassert_equal(BIT(31), NHPOT(BIT(31))); in ZTEST()
28 zassert_equal(BIT64(32), NHPOT(BIT(31) + 1)); in ZTEST()
/Zephyr-Core-3.5.0/subsys/bluetooth/audio/
DKconfig.bap85 range 1 BT_ISO_MAX_CHAN if BT_ISO_MAX_CHAN < 31
86 range 1 31
131 range 1 BT_ISO_MAX_CHAN if BT_ISO_MAX_CHAN < 31
132 range 1 31
150 range 1 BT_ISO_MAX_CHAN if BT_ISO_MAX_CHAN < 31
151 range 1 31
175 range 1 BT_ISO_MAX_CHAN if BT_ISO_MAX_CHAN < 31
176 range 1 31
194 range 1 BT_ISO_MAX_CHAN if BT_ISO_MAX_CHAN < 31
195 range 1 31
[all …]
/Zephyr-Core-3.5.0/include/zephyr/drivers/usb_c/
Dusbc_tc.h161 * See Table 4-31 CC Timing
167 * See Table 4-31 CC Timing
174 * See Table 4-31 CC Timing
181 * See Table 4-31 CC Timing
188 * See Table 4-31 CC Timing
195 * See Table 4-31 CC Timing
201 * See Table 4-31 CC Timing
208 * See Table 4-31 CC Timing
215 * See Table 4-31 CC Timing
222 * See Table 4-31 CC Timing
[all …]
/Zephyr-Core-3.5.0/drivers/rtc/
Drtc_emul.c53 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
57 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
94 (timeptr->tm_mday < 1 || timeptr->tm_mday > 31)) { in rtc_emul_validate_alarm_time()
/Zephyr-Core-3.5.0/tests/unit/timeutil/
Dtest_s64.c52 .civil = "3999-12-31 23:59:59 Fri 365",
57 .tm_mday = 31,
77 .civil = "1899-12-31 23:59:59 Sun 365",
82 .tm_mday = 31,
125 .civil = "1900-12-31 00:00:00 Mon 365",
130 .tm_mday = 31,
153 .civil = "-1-12-31 00:00:00 Fri 365",
158 .tm_mday = 31,
177 .civil = "0-12-31 23:59:59 Sun 366",
182 .tm_mday = 31,
[all …]
Dtest_s32.c15 .civil = "1969-12-31 23:59:59 Wed 365",
20 .tm_mday = 31,
82 .civil = "1971-12-31 23:59:59 Fri 365",
87 .tm_mday = 31,
154 .civil = "1972-12-31 00:00:00 Sun 366",
159 .tm_mday = 31,
180 .civil = "1999-12-31 23:59:59 Fri 365",
185 .tm_mday = 31,
/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h27 * @param src is the interrupt source in the GIRQ (0 - 31)
43 * @param src is the interrupt source in the GIRQ (0 - 31)
63 * @param src is the interrupt source in the GIRQ (0 - 31)
84 * @param src is the interrupt source in the GIRQ (0 - 31)
95 * @param src is the interrupt source in the GIRQ (0 - 31)
103 * @param src is the interrupt source in the GIRQ (0 - 31)
118 * @param src_bit is the source bit position in the GIRQ registers (0 - 31)
125 * @param src_bit is the source bit position in the GIRQ registers (0 - 31)
132 * @param src_bit is the source bit position in the GIRQ registers (0 - 31)
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/
Dadsp_ipc_regs.h35 uint32_t unused3[31];
39 #define INTEL_ADSP_IPC_BUSY BIT(31)
40 #define INTEL_ADSP_IPC_DONE BIT(31)
45 * On ACE SoC family boards TDA bit 31 (BUSY) during IPC doorbell acknowledgment
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/
Dadsp_ipc_regs.h35 uint32_t unused3[31];
39 #define INTEL_ADSP_IPC_BUSY BIT(31)
40 #define INTEL_ADSP_IPC_DONE BIT(31)
45 * On ACE SoC family boards TDA bit 31 (BUSY) during IPC doorbell acknowledgment
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/
Dsoc_pcr.h14 /* slp_idx = [0, 4], bitpos = [0, 31] refer above */
36 #define MCHP_XEC_CLK_SRC_MASK GENMASK(31, 24)
45 * b[31:24] = clock source
/Zephyr-Core-3.5.0/boards/arm/nrf52840dongle_nrf52840/
Dnrf52840dongle_nrf52840-pinctrl.dtsi47 <NRF_PSEL(TWIM_SCL, 0, 31)>;
54 <NRF_PSEL(TWIM_SCL, 0, 31)>;
96 psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
104 psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/
Dadsp_ipc_regs.h27 #define INTEL_ADSP_IPC_BUSY BIT(31)
28 #define INTEL_ADSP_IPC_DONE BIT(31)
/Zephyr-Core-3.5.0/dts/arm/st/g0/
Dstm32g0_crypt.dtsi17 interrupts = <31 0>;
24 interrupts = <31 1>;
/Zephyr-Core-3.5.0/arch/arm/core/mmu/
Darm_mmu_priv.h102 uint32_t base_address : 12; /* [31] */
111 uint32_t l2_page_table_address : 22; /* [31] */
115 uint32_t reserved : 30; /* [31] */
134 uint32_t pa_base : 20; /* [31] */
147 uint32_t pa_base : 16; /* [31] */
151 uint32_t reserved : 30; /* [31] */
/Zephyr-Core-3.5.0/boards/shields/buydisplay_2_8_tft_touch_arduino/
Dbuydisplay_2_8_tft_touch_arduino.overlay41 pgamctrl = [0f 31 2b 0c 0e 08 4e f1 37 07 10 03 0e 09 00];
42 ngamctrl = [00 0e 14 03 11 07 31 c1 48 08 0f 0c 31 36 0f];
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml19 * Bank 0: MIO pins [31:00]
21 * Bank 2: EMIO pins [31:00]
28 * Bank 3: EMIO pins [31:00]
/Zephyr-Core-3.5.0/samples/subsys/debug/fuzz/
DREADME.rst57 …#418965 REDUCE cov: 165 ft: 166 corp: 15/400b lim: 4052 exec/s: 38087 rss: 31Mb L: 5/256 MS: 1 Era…
58 #524288 pulse cov: 165 ft: 166 corp: 15/400b lim: 4096 exec/s: 40329 rss: 31Mb
63 …#579131 NEW cov: 168 ft: 169 corp: 16/406b lim: 4096 exec/s: 38608 rss: 31Mb L: 6/256 MS: 1 Ins…
64 …#579432 NEW cov: 170 ft: 171 corp: 17/414b lim: 4096 exec/s: 38628 rss: 31Mb L: 8/256 MS: 1 Per…
65 …#579948 REDUCE cov: 170 ft: 171 corp: 17/413b lim: 4096 exec/s: 38663 rss: 31Mb L: 7/256 MS: 1 Era…
/Zephyr-Core-3.5.0/boards/arm/raytac_mdbt53v_db_40_nrf5340/
Draytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi10 psels = <NRF_PSEL(UART_TX, 0, 31)>,
19 psels = <NRF_PSEL(UART_TX, 0, 31)>,
/Zephyr-Core-3.5.0/boards/arm/ubx_bmd300eval_nrf52832/
Dubx_bmd300eval_nrf52832-pinctrl.dtsi44 <NRF_PSEL(TWIM_SCL, 0, 31)>;
51 <NRF_PSEL(TWIM_SCL, 0, 31)>;
89 psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
97 psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
/Zephyr-Core-3.5.0/boards/arm/nrf52dk_nrf52832/
Dnrf52dk_nrf52832-pinctrl.dtsi44 <NRF_PSEL(TWIM_SCL, 0, 31)>;
51 <NRF_PSEL(TWIM_SCL, 0, 31)>;
89 psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
97 psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,

12345678910>>...35