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/Zephyr-latest/tests/drivers/can/api/src/
Dcommon.h5 * SPDX-License-Identifier: Apache-2.0
33 * @brief Standard (11-bit) CAN IDs and masks used for testing.
43 * @brief Extended (29-bit) CAN IDs and masks used for testing.
61 * @brief Standard (11-bit) CAN ID frame 1.
66 * @brief Standard (11-bit) CAN ID frame 2.
71 * @brief Extended (29-bit) CAN ID frame 1.
76 * @brief Extended (29-bit) CAN ID frame 1.
81 * @brief Standard (11-bit) CAN ID RTR frame 1.
86 * @brief Extended (29-bit) CAN ID RTR frame 1.
92 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
[all …]
Dcommon.c5 * SPDX-License-Identifier: Apache-2.0
26 * @brief Standard (11-bit) CAN ID frame 1.
36 * @brief Standard (11-bit) CAN ID frame 2.
46 * @brief Extended (29-bit) CAN ID frame 1.
56 * @brief Extended (29-bit) CAN ID frame 1.
66 * @brief Standard (11-bit) CAN ID RTR frame 1.
76 * @brief Extended (29-bit) CAN ID RTR frame 1.
87 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
94 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
101 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
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Dutilities.c5 * SPDX-License-Identifier: Apache-2.0
75 /* Standard (11-bit) frames and filters */ in ZTEST()
85 /* Extended (29-bit) frames and filters */ in ZTEST()
95 /* Standard (11-bit) frames and extended (29-bit) filters */ in ZTEST()
102 /* Extended (29-bit) frames and standard (11-bit) filters */ in ZTEST()
/Zephyr-latest/drivers/can/
DKconfig.stm324 # Copyright (c) 2018-2020 Alexander Wachter
5 # SPDX-License-Identifier: Apache-2.0
18 int "Maximum number of standard (11-bit) ID filters"
22 Defines the maximum number of filters with standard ID (11-bit)
34 int "Maximum number of extended (29-bit) ID filters"
38 Defines the maximum number of filters with extended ID (29-bit)
62 int "Maximum number of standard (11-bit) ID filters"
66 Defines the maximum number of filters with standard ID (11-bit)
70 int "Maximum number of extended (29-bit) ID filters"
74 Defines the maximum number of filters with extended ID (29-bit)
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
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/Zephyr-latest/samples/drivers/can/babbling/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
15 bool "Use Extended (29-bit) CAN ID"
17 Babling node sends extended (29-bit) CAN ID frames.
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
55 #define SSCR0_EFRDC BIT(27)
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Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
48 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_ACS BIT(30)
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/Zephyr-latest/include/zephyr/net/
Dsocketcan_utils.h10 * SPDX-License-Identifier: Apache-2.0
40 zframe->flags |= (sframe->can_id & BIT(31)) != 0 ? CAN_FRAME_IDE : 0; in socketcan_to_can_frame()
41 zframe->flags |= (sframe->can_id & BIT(30)) != 0 ? CAN_FRAME_RTR : 0; in socketcan_to_can_frame()
42 zframe->flags |= (sframe->flags & CANFD_FDF) != 0 ? CAN_FRAME_FDF : 0; in socketcan_to_can_frame()
43 zframe->flags |= (sframe->flags & CANFD_BRS) != 0 ? CAN_FRAME_BRS : 0; in socketcan_to_can_frame()
44 zframe->id = sframe->can_id & BIT_MASK(29); in socketcan_to_can_frame()
45 zframe->dlc = can_bytes_to_dlc(sframe->len); in socketcan_to_can_frame()
47 if ((zframe->flags & CAN_FRAME_RTR) == 0U) { in socketcan_to_can_frame()
48 memcpy(zframe->data, sframe->data, in socketcan_to_can_frame()
49 MIN(sframe->len, MIN(sizeof(sframe->data), sizeof(zframe->data)))); in socketcan_to_can_frame()
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/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Darm-gic.h4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/dt-util.h>
16 #define GIC_INT_PHYS_TIMER 29
20 /* BIT(0) reserved for IRQ_ZERO_LATENCY */
21 #define IRQ_TYPE_LEVEL BIT(1)
22 #define IRQ_TYPE_EDGE BIT(2)
/Zephyr-latest/include/zephyr/arch/arm64/
Dcpu.h4 * SPDX-License-Identifier: Apache-2.0
13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
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/Zephyr-latest/drivers/ethernet/
Deth_gecko_priv.h5 * SPDX-License-Identifier: Apache-2.0
29 #define ETH_TX_USED BIT(31)
30 #define ETH_TX_WRAP BIT(30)
31 #define ETH_TX_ERROR BIT(29)
32 #define ETH_TX_UNDERRUN BIT(28)
33 #define ETH_TX_EXHAUSTED BIT(27)
34 #define ETH_TX_NO_CRC BIT(16)
35 #define ETH_TX_LAST BIT(15)
36 #define ETH_TX_LENGTH (2048-1)
38 #define ETH_RX_ADDRESS ~(ETH_DESC_ALIGNMENT-1)
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Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
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Doa_tc6.h4 * SPDX-License-Identifier: Apache-2.0
21 #define OA_RESET_SWRESET BIT(0)
23 #define OA_CONFIG0_SYNC BIT(15)
24 #define OA_CONFIG0_RFA_ZARFE BIT(12)
25 #define OA_CONFIG0_PROTE BIT(5)
27 #define OA_STATUS0_RESETC BIT(6)
33 #define OA_IMASK0_TXPEM BIT(0)
34 #define OA_IMASK0_TXBOEM BIT(1)
35 #define OA_IMASK0_TXBUEM BIT(2)
36 #define OA_IMASK0_RXBOEM BIT(3)
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Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
28 #define ADIN2111_RESET_SWRESET BIT(0)
33 #define ADIN2111_CONFIG0_SYNC BIT(15)
35 #define ADIN2111_CONFIG0_TXFCSVE BIT(14)
37 #define ADIN2111_CONFIG0_ZARFE BIT(12)
39 #define ADIN2111_CONFIG0_CSARFE BIT(13)
41 #define ADIN2111_CONFIG0_TXCTE BIT(9)
43 #define ADIN2111_CONFIG0_RXCTE BIT(8)
48 #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14)
50 #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13)
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Ddmic_regs_ace3x.h3 * SPDX-License-Identifier: Apache-2.0
16 #define DMICSYNC_SYNCPU BIT(20)
19 #define DMICSYNC_SYNCGO BIT(23)
22 #define DMICSYNC_CMDSYNC BIT(24)
31 #define DMICLCTL_OFLEN BIT(4)
34 #define DMICLCTL_INTEN BIT(5)
37 #define DMICLCTL_SPA BIT(16)
40 #define DMICLCTL_CPA BIT(23)
43 #define DMICLCTL_INTSTS BIT(31)
49 #define DMICLVSCTL_FCG BIT(26)
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/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
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/Zephyr-latest/drivers/usb/common/
Dusb_dwc2_hw.h5 * SPDX-License-Identifier: Apache-2.0
123 * used to get/set a bitfield consisting of only one bit.
158 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS BIT(USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS)
160 #define USB_DWC2_GAHBCFG_AHBSINGLE BIT(USB_DWC2_GAHBCFG_AHBSINGLE_POS)
162 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT BIT(USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS)
164 #define USB_DWC2_GAHBCFG_REMMEMSUPP BIT(USB_DWC2_GAHBCFG_REMMEMSUPP_POS)
166 #define USB_DWC2_GAHBCFG_PTXFEMPLVL BIT(USB_DWC2_GAHBCFG_PTXFEMPLVL_POS)
168 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL BIT(USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS)
170 #define USB_DWC2_GAHBCFG_DMAEN BIT(USB_DWC2_GAHBCFG_DMAEN_POS)
179 #define USB_DWC2_GAHBCFG_GLBINTRMASK BIT(USB_DWC2_GAHBCFG_GLBINTRMASK_POS)
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Ddmic_regs_ace2x.h1 /* SPDX-License-Identifier: Apache-2.0 */
18 #define DMICSYNC_SYNCPU BIT(20)
21 #define DMICSYNC_SYNCGO BIT(23)
24 #define DMICSYNC_CMDSYNC BIT(24)
34 #define DMICLCTL_OFLEN BIT(4)
37 #define DMICLCTL_INTEN BIT(5)
40 #define DMICLCTL_SPA BIT(16)
43 #define DMICLCTL_CPA BIT(23)
46 #define DMICLCTL_INTSTS BIT(31)
53 #define DMICLVSCTL_FCG BIT(26)
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/Zephyr-latest/include/zephyr/drivers/can/
Dcan_mcan.h5 * SPDX-License-Identifier: Apache-2.0
41 /* Data Bit Timing & Prescaler register */
43 #define CAN_MCAN_DBTP_TDC BIT(23)
51 #define CAN_MCAN_TEST_SVAL BIT(21)
53 #define CAN_MCAN_TEST_PVAL BIT(13)
55 #define CAN_MCAN_TEST_RX BIT(7)
57 #define CAN_MCAN_TEST_LBCK BIT(4)
66 #define CAN_MCAN_CCCR_NISO BIT(15)
67 #define CAN_MCAN_CCCR_TXP BIT(14)
68 #define CAN_MCAN_CCCR_EFBI BIT(13)
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
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/Zephyr-latest/soc/renesas/rzt2m/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
16 #define CNTCR_EN BIT(0)
17 #define CNTCR_HDBG BIT(1)
20 #define PRCRS_CLK BIT(0)
21 #define PRCRS_LPC_RESET BIT(1)
22 #define PRCRS_GPIO BIT(2)
23 #define PRCRS_SYS_CTRL BIT(3)
25 /* Non-safety area protect register */
26 #define PRCRN_PRC0 BIT(0)
27 #define PRCRN_PRC1 BIT(1)
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/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_adc.h4 * SPDX-License-Identifier: Apache-2.0
14 /* 16 ADC channels numbered 0 - 15 */
18 /* Eight ADC channels numbered 0 - 7 */
28 #define MCHP_ADC_CTRL_ACTV BIT(0)
29 #define MCHP_ADC_CTRL_START_SNGL BIT(1)
30 #define MCHP_ADC_CTRL_START_RPT BIT(2)
31 #define MCHP_ADC_CTRL_PWRSV_DIS BIT(3)
32 #define MCHP_ADC_CTRL_SRST BIT(4)
33 #define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */
34 #define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */
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