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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h57 #define PIN_CLKOUT RCAR_GP_PIN(1, 28)
161 #define PIN_USB30_PWEN RCAR_GP_PIN(6, 28)
196 #define PIN_QSPI0_SPCLK RCAR_NOGP_PIN(28)
239 #define FUNC_IRQ1 IPSR(0, 28, 0)
240 #define FUNC_QPOLA IPSR(0, 28, 1)
241 #define FUNC_DU_DISP IPSR(0, 28, 3)
242 #define FUNC_VI4_DATA1_B IPSR(0, 28, 4)
243 #define FUNC_CAN0_RX_B IPSR(0, 28, 5)
244 #define FUNC_CANFD0_RX_B IPSR(0, 28, 6)
245 #define FUNC_MSIOF3_SS1_E IPSR(0, 28, 7)
[all …]
Dpinctrl-r8a77961.h75 #define FUNC_SD1_DAT3 IPSR(8, 28, 0)
88 #define FUNC_SD2_DAT7 IPSR(8, 28, 1)
95 #define FUNC_SD3_CLK IPSR(9, 28, 0)
103 #define FUNC_SD3_DAT6 IPSR(10, 28, 0)
105 #define FUNC_SD3_CD IPSR(10, 28, 1)
/Zephyr-Core-3.5.0/drivers/can/
DKconfig.stm3219 range 0 28
30 CAN_MAX_STD_ID_FILTER + CAN_MAX_EXT_ID_FILTER * 2 <= 28
46 CAN_MAX_STD_ID_FILTER + CAN_MAX_EXT_ID_FILTER * 2 <= 28
61 default 28
62 range 0 28
Dcan_mcp251xfd.h86 #define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)
162 #define MCP251XFD_REG_INT_SERRIE BIT(28)
217 #define MCP251XFD_REG_BDIAG1_DSTUFERR BIT(28)
239 #define MCP251XFD_REG_TEFCON_FSIZE_MASK GENMASK(28, 24)
266 #define MCP251XFD_REG_TXQCON_FSIZE_MASK GENMASK(28, 24)
301 #define MCP251XFD_REG_FIFOCON_FSIZE_MASK GENMASK(28, 24)
339 #define MCP251XFD_REG_FLTOBJ_EID_MASK GENMASK(28, 11)
345 #define MCP251XFD_REG_MASK_MEID_MASK GENMASK(28, 11)
350 #define MCP251XFD_OBJ_ID_EID_MASK GENMASK(28, 11)
366 #define MCP251XFD_REG_FRAME_EFF_SID_MASK GENMASK(28, 18)
[all …]
/Zephyr-Core-3.5.0/boards/arm/nrf52_blenano2/
Dnrf52_blenano2-pinctrl.dtsi12 <NRF_PSEL(UART_CTS, 0, 28)>;
21 <NRF_PSEL(UART_CTS, 0, 28)>;
28 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
/Zephyr-Core-3.5.0/boards/arm/we_proteus2ev_nrf52832/
Dwe_proteus2ev_nrf52832-pinctrl.dtsi9 <NRF_PSEL(UART_CTS, 0, 28)>;
19 <NRF_PSEL(UART_CTS, 0, 28)>;
41 psels = <NRF_PSEL(SPIM_SCK, 0, 28)>,
49 psels = <NRF_PSEL(SPIM_SCK, 0, 28)>,
/Zephyr-Core-3.5.0/samples/net/sockets/dumb_http_server_mt/
Ddocker-test.sh17 # curl timeout is return code 28. If we get that, zephyr will never
19 if [ $docker_result -eq 28 ]; then
48 # curl timeout is return code 28. If we get that, zephyr will never
50 if [ $docker_result -eq 28 ]; then
/Zephyr-Core-3.5.0/soc/arm64/renesas_rcar/gen3/
Dpfc_r8a77951.c14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
[all …]
/Zephyr-Core-3.5.0/soc/arm/renesas_rcar/gen3/
Dpfc_r8a77951.c14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
[all …]
/Zephyr-Core-3.5.0/samples/net/zperf/
Dprj.conf13 CONFIG_NET_BUF_RX_COUNT=28
14 CONFIG_NET_BUF_TX_COUNT=28
/Zephyr-Core-3.5.0/samples/subsys/zbus/msg_subscriber/
DREADME.rst33 I: AL Memory allocated 28 bytes. Total allocated 28 bytes
50 I: FR Memory freed 28 bytes. Total allocated 0 bytes
55 I: AL Memory allocated 28 bytes. Total allocated 28 bytes
72 I: FR Memory freed 28 bytes. Total allocated 0 bytes
/Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32/
Desp32_wrover_e_n8r8.dtsi11 gpio-reserved-ranges = <20>, <24>, <28 31>;
13 <20>,<24>,<28 31>; // NC
/Zephyr-Core-3.5.0/boards/arm/bl5340_dvk/
Dbl5340_dvk_cpuapp_common-pinctrl.dtsi26 <NRF_PSEL(SPIM_SCK, 0, 28)>;
34 <NRF_PSEL(SPIM_SCK, 0, 28)>;
94 psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
100 psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
/Zephyr-Core-3.5.0/dts/bindings/dsa/
Dmicrochip,ksz8794.yaml23 Supported values 2,4,8,12,16,20,24,28mA
33 - 28
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dquicklogic,eos-s3-gpio.yaml24 "2 : 11 / 28"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
136 #define MIO28 28
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
234 #define MIO_GROUP_CAN1_5_GRP_PINS 28, 29
257 #define MIO_GROUP_UART1_5_GRP_PINS 28, 29
[all …]
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h51 #define APL_GPIO_28 28
85 #define APL_GPIO_72 28
135 #define APL_GPIO_215 28
169 #define APL_GPIO_FST_SPI_CLK_FB 28
218 #define APL_GPIO_211 28
269 #define APL_GPIO_186 28
/Zephyr-Core-3.5.0/boards/arm/96b_carbon_nrf51/
D96b_carbon_nrf51-pinctrl.dtsi9 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
16 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
/Zephyr-Core-3.5.0/boards/arm/ruuvi_ruuvitag/
Druuvi_ruuvitag-pinctrl.dtsi30 <NRF_PSEL(SPIM_MISO, 0, 28)>;
38 <NRF_PSEL(SPIM_MISO, 0, 28)>;
/Zephyr-Core-3.5.0/boards/arm/raytac_mdbt53_db_40_nrf5340/
Draytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi62 psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
68 psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
100 <NRF_PSEL(SPIM_SCK, 0, 28)>;
108 <NRF_PSEL(SPIM_SCK, 0, 28)>;
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-rp2040-pinctrl.h59 #define UART0_TX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART)
90 #define I2C0_SDA_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C)
121 #define PWM_6A_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM)
152 #define SPI1_RX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI)
157 #define ADC_CH2_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL)
188 #define PIO0_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO0)
219 #define PIO1_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO1)
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt5xx/
Dpower.c28 isp_pin[1] = IOPCTL->PIO[3][28]; in set_deepsleep_pin_config()
33 IOPCTL->PIO[3][28] = 0; in set_deepsleep_pin_config()
41 IOPCTL->PIO[3][28] = isp_pin[1]; in restore_deepsleep_pin_config()
/Zephyr-Core-3.5.0/boards/arm/cc1352r1_launchxl/
Dboosterpack_connector.dtsi29 <26 0 &gpio0 28 0>,
31 <28 0 &gpio0 30 0>,
/Zephyr-Core-3.5.0/boards/arm/nrf52833dk_nrf52820/
Dnrf52833dk_nrf52820-pinctrl.dtsi31 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
38 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
/Zephyr-Core-3.5.0/boards/arm/pan1781_evb/
Dpan1781_evb-pinctrl.dtsi49 psels = <NRF_PSEL(SPIM_SCK, 0, 28)>,
57 psels = <NRF_PSEL(SPIM_SCK, 0, 28)>,

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