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/Zephyr-latest/samples/userspace/shared_mem/src/
Denc.h13 #define WHEEL_SIZE 26
26 extern volatile BYTE W1[26];
27 extern volatile BYTE W2[26];
28 extern volatile BYTE W3[26];
29 extern volatile BYTE R[26];
30 extern volatile BYTE W1R[26];
31 extern volatile BYTE W2R[26];
32 extern volatile BYTE W3R[26];
/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml43 - "Input\\[26\\]: 17 18 19 20 21 22 23 24 25 26 | Output\\[26\\]: 21.50"
44 - "Input\\[27\\]: 18 19 20 21 22 23 24 25 26 27 | Output\\[27\\]: 22.50"
45 - "Input\\[28\\]: 19 20 21 22 23 24 25 26 27 28 | Output\\[28\\]: 23.50"
46 - "Input\\[29\\]: 20 21 22 23 24 25 26 27 28 29 | Output\\[29\\]: 24.50"
47 - "Input\\[30\\]: 21 22 23 24 25 26 27 28 29 30 | Output\\[30\\]: 25.50"
48 - "Input\\[31\\]: 22 23 24 25 26 27 28 29 30 31 | Output\\[31\\]: 26.50"
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h26 * @param girq_id is the GIRQ number (8 - 26)
42 * @param girq_id is the GIRQ number (8 - 26)
62 * @param girq_id is the GIRQ number (8 - 26)
94 * @param girq_id is the GIRQ number (8 - 26)
110 * @param girq_id is the GIRQ number (8 - 26)
117 * @param girq_id is the GIRQ number (8 - 26)
124 * @param girq_id is the GIRQ number (8 - 26)
131 * @param girq_id is the GIRQ number (8 - 26)
138 * @param girq_id is the GIRQ number (8 - 26)
145 * @param girq_id is the GIRQ number (8 - 26)
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
55 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
67 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
/Zephyr-latest/boards/sparkfun/nrf52_sparkfun/
Dnrf52_sparkfun-pinctrl.dtsi10 <NRF_PSEL(UART_RX, 0, 26)>;
17 <NRF_PSEL(UART_RX, 0, 26)>;
/Zephyr-latest/boards/nordic/nrf52840dongle/
Dnrf52840dongle_nrf52840-pinctrl.dtsi31 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
38 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
80 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
88 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-latest/dts/bindings/gpio/
Drenesas,mipi-header.yaml9 This binding provides a mapping for the default 26 pins as depicted below:
23 13 GND 5V0 26
Draspberrypi,pico-header.yaml9 This binding provides a nexus mapping for the default 26 pins as depicted below:
20 7 GPIO7 GPIO26/ADC0 26
/Zephyr-latest/soc/mediatek/mt8xxx/
Dcpuclk.c13 * * power-on default is 26Mhz, confirmed with a hacked SOF that
16 * hits all the same code and data paths as 26MHz and acts as a
64 { 26, false, 0 },
138 /* Switch to PLL from 26Mhz */ in mtk_adsp_set_cpu_freq()
144 /* Switch to 26Mhz from PLL */ in mtk_adsp_set_cpu_freq()
154 * the speed we're at (on MT8195, hardware powers up at 26 Mhz, but
/Zephyr-latest/dts/arm/st/f7/
Dstm32f746.dtsi19 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
20 resets = <&rctl STM32_RESET(APB2, 26U)>;
Dstm32f767.dtsi20 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
21 resets = <&rctl STM32_RESET(APB2, 26U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4r9.dtsi20 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
21 resets = <&rctl STM32_RESET(APB2, 26U)>;
/Zephyr-latest/boards/croxel/croxel_cx1825/
Dcroxel_cx1825_nrf52840-pinctrl.dtsi11 <NRF_PSEL(TWIM_SCL, 0, 26)>;
18 <NRF_PSEL(TWIM_SCL, 0, 26)>;
/Zephyr-latest/boards/u-blox/ubx_bmd300eval/
Dubx_bmd300eval_nrf52832-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
73 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
81 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-latest/boards/raytac/mdbt50q_db_33/
Draytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi49 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
94 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
102 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-latest/boards/nordic/nrf52dk/
Dnrf52dk_nrf52832-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
73 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
81 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-latest/boards/ezurio/bt510/
Dbt510-pinctrl.dtsi24 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
31 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-latest/doc/connectivity/networking/
Dzephyr_netstack_overview.svg10 <v:ud v:nameU="msvNoAutoConnect" v:val="VT0(1):26"/>
41 <v:ud v:nameU="msvThemeOrder" v:val="VT0(0):26"/>
50 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
64 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
78 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
92 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
105 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
120 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
134 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
148 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
[all …]
/Zephyr-latest/boards/ezurio/pinnacle_100_dvk/
Dpinnacle_100_dvk-pinctrl.dtsi47 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
63 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
71 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-latest/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdew042t2.overlay33 pwr = [03 00 26 26 09];
/Zephyr-latest/dts/arm/st/f4/
Dstm32f429.dtsi27 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
28 resets = <&rctl STM32_RESET(APB2, 26U)>;
/Zephyr-latest/soc/intel/apollo_lake/
Dsoc_gpio.h49 #define APL_GPIO_26 26
83 #define APL_GPIO_70 26
133 #define APL_GPIO_213 26
167 #define APL_GPIO_102 26
216 #define APL_GPIO_209 26
267 #define APL_GPIO_177 26
/Zephyr-latest/samples/sensor/icm42605/boards/
Dnrf52dk_nrf52832.overlay11 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
19 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-latest/boards/vngiotlab/nrf52_vbluno52/
Dnrf52_vbluno52-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-latest/boards/nordic/nrf52833dk/
Dnrf52833dk_nrf52833-pinctrl.dtsi49 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
94 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
102 <NRF_PSEL(SPIM_MOSI, 0, 26)>,

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