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/Zephyr-Core-3.6.0/samples/userspace/shared_mem/src/
Denc.h13 #define WHEEL_SIZE 26
26 extern volatile BYTE W1[26];
27 extern volatile BYTE W2[26];
28 extern volatile BYTE W3[26];
29 extern volatile BYTE R[26];
30 extern volatile BYTE W1R[26];
31 extern volatile BYTE W2R[26];
32 extern volatile BYTE W3R[26];
Dmain.c50 volatile _app_enc_d BYTE W1[26] = START_WHEEL;
52 volatile _app_enc_d BYTE W1[26] = START_WHEEL2;
54 volatile _app_enc_d BYTE W2[26] = START_WHEEL;
55 volatile _app_enc_d BYTE W3[26] = START_WHEEL;
56 volatile _app_enc_d BYTE R[26] = REFLECT;
66 volatile _app_enc_b BYTE W1R[26];
67 volatile _app_enc_b BYTE W2R[26];
68 volatile _app_enc_b BYTE W3R[26];
/Zephyr-Core-3.6.0/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h26 * @param girq_id is the GIRQ number (8 - 26)
42 * @param girq_id is the GIRQ number (8 - 26)
62 * @param girq_id is the GIRQ number (8 - 26)
94 * @param girq_id is the GIRQ number (8 - 26)
110 * @param girq_id is the GIRQ number (8 - 26)
117 * @param girq_id is the GIRQ number (8 - 26)
124 * @param girq_id is the GIRQ number (8 - 26)
131 * @param girq_id is the GIRQ number (8 - 26)
138 * @param girq_id is the GIRQ number (8 - 26)
145 * @param girq_id is the GIRQ number (8 - 26)
[all …]
/Zephyr-Core-3.6.0/soc/riscv/sifive_freedom/u700/
Dclock.c26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in fu740_clock_init()
40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in fu740_clock_init()
51 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in fu740_clock_init()
54 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in fu740_clock_init()
65 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in fu740_clock_init()
/Zephyr-Core-3.6.0/boards/arm/nrf52_sparkfun/
Dnrf52_sparkfun-pinctrl.dtsi10 <NRF_PSEL(UART_RX, 0, 26)>;
17 <NRF_PSEL(UART_RX, 0, 26)>;
/Zephyr-Core-3.6.0/boards/arm/nrf52840dongle_nrf52840/
Dnrf52840dongle_nrf52840-pinctrl.dtsi31 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
38 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
80 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
88 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt50q_db_33_nrf52833/
Draytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi49 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
94 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
102 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/nrf52dk_nrf52832/
Dnrf52dk_nrf52832-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
73 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
81 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/ubx_bmd300eval_nrf52832/
Dubx_bmd300eval_nrf52832-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
73 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
81 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/doc/connectivity/networking/
Dzephyr_netstack_overview.svg10 <v:ud v:nameU="msvNoAutoConnect" v:val="VT0(1):26"/>
41 <v:ud v:nameU="msvThemeOrder" v:val="VT0(0):26"/>
50 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
64 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
78 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
92 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
105 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
120 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
134 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
148 <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
[all …]
/Zephyr-Core-3.6.0/boards/arm/bt510/
Dbt510-pinctrl.dtsi24 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
31 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-Core-3.6.0/dts/bindings/gpio/
Draspberrypi,pico-header.yaml9 This binding provides a nexus mapping for the default 26 pins as depicted below:
20 7 GPIO7 GPIO26/ADC0 26
/Zephyr-Core-3.6.0/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdew042t2.overlay28 pwr = [03 00 26 26 09];
/Zephyr-Core-3.6.0/boards/arm/pinnacle_100_dvk/
Dpinnacle_100_dvk-pinctrl.dtsi47 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
63 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
71 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/soc/x86/apollo_lake/
Dsoc_gpio.h49 #define APL_GPIO_26 26
83 #define APL_GPIO_70 26
133 #define APL_GPIO_213 26
167 #define APL_GPIO_102 26
216 #define APL_GPIO_209 26
267 #define APL_GPIO_177 26
/Zephyr-Core-3.6.0/boards/arm/nrf52_vbluno52/
Dnrf52_vbluno52-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-Core-3.6.0/samples/sensor/icm42605/boards/
Dnrf52dk_nrf52832.overlay11 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
19 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/nrf52833dk_nrf52833/
Dnrf52833dk_nrf52833-pinctrl.dtsi49 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
94 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
102 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/nrf52_adafruit_feather/
Dnrf52_adafruit_feather-pinctrl.dtsi25 <NRF_PSEL(TWIM_SCL, 0, 26)>;
32 <NRF_PSEL(TWIM_SCL, 0, 26)>;
/Zephyr-Core-3.6.0/samples/drivers/i2s/echo/boards/
Dnrf5340dk_nrf5340_cpuapp.overlay11 <NRF_PSEL(TWIM_SCL, 0, 26)>;
18 <NRF_PSEL(TWIM_SCL, 0, 26)>;
/Zephyr-Core-3.6.0/boards/arm/nrf21540dk_nrf52840/
Dnrf21540dk_nrf52840-pinctrl.dtsi49 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
94 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
102 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/particle_argon/dts/
Dmesh_feather-pinctrl.dtsi9 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
16 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/particle_xenon/dts/
Dmesh_feather-pinctrl.dtsi9 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
16 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/bl654_sensor_board/
Dbl654_sensor_board-pinctrl.dtsi28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
/Zephyr-Core-3.6.0/boards/arm/particle_boron/dts/
Dmesh_feather-pinctrl.dtsi9 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
16 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,

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