| /Zephyr-latest/dts/arm/infineon/cat3/xmc/ |
| D | xmc4700_F144x2048-intc.dtsi | 11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
18 XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */
20 XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */
21 XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */
22 XMC4XXX_INTC_SET_LINE_MAP(0, 13, 2, 2) /* ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 */
23 XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */
24 XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
[all …]
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| D | xmc4500_F100x1024-intc.dtsi | 11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
18 XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */
20 XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */
21 XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */
22 XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */
23 XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
24 XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */
[all …]
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| /Zephyr-latest/boards/shields/st7735r/ |
| D | st7735r_ada_160x128.overlay | 37 pwctr4 = [8a 2a];
39 frmctr1 = [01 2c 2d];
40 frmctr2 = [01 2c 2d];
41 frmctr3 = [01 2c 2d 01 2c 2d];
42 gamctrp1 = [02 1c 07 12 37 32 29 2d 29 25 2b 39 00 01 03 10];
43 gamctrn1 = [03 1d 07 06 2e 2c 29 2d 2e 2e 37 3f 00 00 02 10];
|
| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_hs_hostlink.props | 2 nsim_isa_core=2
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
31 nsim_isa_number_of_levels=2
35 dcache=65536,64,2,a
36 nsim_isa_dc_feature_level=2
38 nsim_isa_dc_mem_cycles=2
40 nsim_isa_ic_feature_level=2
[all …]
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| D | nsim_em.props | 4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
12 nsim_isa_code_density_option=2
20 mpu_version=2
21 nsim_isa_dsp_option=2
26 nsim_isa_dsp_accshift_option=2
45 nsim_isa_num_actionpoints=2
54 dcache=16384,32,2,a
55 nsim_isa_dc_feature_level=2
56 icache=16384,32,2,a
[all …]
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| D | nsim_hs.props | 2 nsim_isa_core=2
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
31 nsim_isa_number_of_levels=2
35 dcache=65536,64,2,a
36 nsim_isa_dc_feature_level=2
38 nsim_isa_dc_mem_cycles=2
40 nsim_isa_ic_feature_level=2
[all …]
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| D | nsim_hs_mpuv6.props | 2 nsim_isa_core=2
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
33 nsim_isa_number_of_levels=2
37 dcache=65536,64,2,a
38 nsim_isa_dc_feature_level=2
40 nsim_isa_dc_mem_cycles=2
42 nsim_isa_ic_feature_level=2
[all …]
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| D | nsim_hs_flash_xip.props | 2 nsim_isa_core=2
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
31 nsim_isa_number_of_levels=2
35 dcache=65536,64,2,a
36 nsim_isa_dc_feature_level=2
38 nsim_isa_dc_mem_cycles=2
40 nsim_isa_ic_feature_level=2
|
| D | nsim_hs_sram.props | 2 nsim_isa_core=2
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
31 nsim_isa_number_of_levels=2
35 dcache=65536,64,2,a
36 nsim_isa_dc_feature_level=2
38 nsim_isa_dc_mem_cycles=2
40 nsim_isa_ic_feature_level=2
|
| D | nsim_em7d_v22.props | 2 nsim_isa_core=2
11 nsim_isa_code_density_option=2
18 nsim_isa_dsp_option=2
31 nsim_isa_num_actionpoints=2
36 mpu_version=2
42 dcache=16384,32,2,a
43 nsim_isa_dc_feature_level=2
44 icache=16384,32,2,a
45 nsim_isa_ic_feature_level=2
53 nsim_isa_dmac_channels=2
[all …]
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| D | nsim_em11d.props | 7 nsim_isa_rgf_num_wr_ports=2
12 nsim_isa_code_density_option=2
20 mpu_version=2
21 nsim_isa_dsp_option=2
26 nsim_isa_dsp_accshift_option=2
46 nsim_isa_num_actionpoints=2
55 dcache=16384,32,2,a
56 nsim_isa_dc_feature_level=2
57 icache=16384,32,2,a
58 nsim_isa_ic_feature_level=2
[all …]
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| D | nsim_vpx5.props | 6 nsim_isa_code_density_option=2
9 nsim_isa_rgf_num_wr_ports=2
17 nsim_isa_div_rem_option=2
31 nsim_isa_dmp_peripheral_version=2
44 nsim_bpu_fb_entries=2
50 dcache=32768,64,2,a
52 nsim_isa_dc_feature_level=2
56 nsim_isa_ic_feature_level=2
64 nsim_connect=2
65 nsim_connect_asi=2
[all …]
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| D | mdb_hs_smp.args | 3 -rgf_num_banks=2
5 -rgf_num_wr_ports=2
27 -interrupt_priorities=2
30 -dcache=65536,64,2,a
31 -dcache_feature=2
33 -dcache_mem_cycles=2
35 -icache_feature=2
43 -connect_idu=2
46 -connect_icd=2
47 -connect_ici=2
|
| /Zephyr-latest/tests/net/icmp/ |
| D | testcase.yaml | 10 - CONFIG_NET_IF_MAX_IPV6_COUNT=2
11 - CONFIG_NET_IF_MAX_IPV4_COUNT=2
15 - CONFIG_NET_IF_MAX_IPV6_COUNT=2
16 - CONFIG_NET_IF_MAX_IPV4_COUNT=2
20 - CONFIG_NET_IF_MAX_IPV6_COUNT=2
21 - CONFIG_NET_IF_MAX_IPV4_COUNT=2
25 - CONFIG_NET_IF_MAX_IPV6_COUNT=2
26 - CONFIG_NET_IF_MAX_IPV4_COUNT=2
30 - CONFIG_NET_IF_MAX_IPV6_COUNT=2
34 - CONFIG_NET_IF_MAX_IPV4_COUNT=2
|
| /Zephyr-latest/tests/cmake/zephyr_get/ |
| D | CMakeLists.txt | 24 # - run_suite(<test-1> [<test-2> ...])
51 # [IMAGE <image-2> <expected-value-for-image-2> ...]
146 IMAGE zephyr_get_2nd "sysbuild.2nd"
160 IMAGE zephyr_get_2nd "sysbuild.2nd"
180 IMAGE zephyr_get_2nd "sysbuild.2nd"
231 IMAGE zephyr_get_2nd "sysbuild.2nd"
244 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main"
257 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main;cmake cache;environment;local"
266 IMAGE zephyr_get_2nd "sysbuild.2nd;cmake cache;environment"
278 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main;environment"
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ch32v003-pinctrl.h | 12 #define CH32V003_PINMUX_PORT_PD 2
21 #define CH32V003_PINMUX_USART1_RM 2
27 /* Port number with 0-2 */
30 #define CH32V003_PINCTRL_PIN_SHIFT 2
44 #define TIM1_ETR_PD4_2 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 2)
45 #define TIM1_ETR_PC2_3 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 3)
46 #define TIM1_CH1_PD2_0 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 0)
48 #define TIM1_CH1_PD2_2 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 2)
52 #define TIM1_CH2_PA1_2 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 2)
56 #define TIM1_CH3_PC3_2 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 2)
[all …]
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| /Zephyr-latest/drivers/video/ |
| D | mt9m114.c | 83 {0x098E, 2, 0x1000}, /* LOGICAL_ADDRESS_ACCESS */
85 {0xC980, 2, 0x0120}, /* CAM_SYSCTL_PLL_DIVIDER_M_N = 288 */
86 {0xC982, 2, 0x0700}, /* CAM_SYSCTL_PLL_DIVIDER_P = 1792 */
88 {0x316A, 2, 0x8270}, /* Auto txlo_row for hot pixel and linear full well optimization */
89 {0x316C, 2, 0x8270}, /* Auto txlo for hot pixel and linear full well optimization */
90 {0x3ED0, 2, 0x2305}, /* Eclipse setting, ecl range=1, ecl value=2, ivln=3 */
91 {0x3ED2, 2, 0x77CF}, /* TX_hi = 12 */
92 {0x316E, 2, 0x8202}, /* Auto ecl , threshold 2x, ecl=0 at high gain, ecl=2 for low gain */
93 {0x3180, 2, 0x87FF}, /* Enable delta dark */
94 {0x30D4, 2, 0x6080}, /* Disable column correction due to AE oscillation problem */
[all …]
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc11u6x.dtsi | 84 interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \
85 <4 2>, <5 2>, <6 2>, <7 2>;
88 #gpio-cells = <2>;
101 interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \
102 <4 2>, <5 2>, <6 2>, <7 2>;
105 #gpio-cells = <2>;
114 gpio2: gpio@2 {
117 interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \
118 <4 2>, <5 2>, <6 2>, <7 2>;
121 #gpio-cells = <2>;
[all …]
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| /Zephyr-latest/scripts/dts/python-devicetree/tests/ |
| D | test.dts | 23 interrupts = <1 2 3 4 5 6>;
36 #interrupt-cells = <2>;
39 controller-2 {
47 &{/interrupts-extended-test/controller-1} 2 3
48 &{/interrupts-extended-test/controller-2} 4 5 6>;
52 #address-cells = <2>;
63 #address-cells = <2>;
64 #interrupt-cells = <2>;
67 controller-2 {
74 #interrupt-cells = <2>;
[all …]
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| /Zephyr-latest/subsys/net/ip/ |
| D | net_tc_mapping.h | 19 * according to 802.1Q - table I-2.
24 * 2 EE Excellent effort
47 #if NET_TC_TX_COUNT == 2 || NET_TC_RX_COUNT == 2
51 static const uint8_t priority2tc_strict_3[] = {0, 0, 0, 0, 1, 1, 2, 2};
54 static const uint8_t priority2tc_strict_4[] = {0, 0, 1, 1, 2, 2, 3, 3};
57 static const uint8_t priority2tc_strict_5[] = {0, 0, 1, 1, 2, 2, 3, 4};
60 static const uint8_t priority2tc_strict_6[] = {1, 0, 2, 2, 3, 3, 4, 5};
63 static const uint8_t priority2tc_strict_7[] = {1, 0, 2, 3, 4, 4, 5, 6};
66 static const uint8_t priority2tc_strict_8[] = {1, 0, 2, 3, 4, 5, 6, 7};
83 #if NET_TC_TX_COUNT == 2 || NET_TC_RX_COUNT == 2
[all …]
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| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 43 '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3',
47 '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3',
51 '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4',
54 '9', '9', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '2',
55 '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4',
58 '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '2', '2', '2',
59 '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5',
62 '0', '0', '0', '1', '1', '1', '1', '1', '2', '2', '2', '2', '2',
66 '0', '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3',
70 '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3', '3',
[all …]
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-wui-map.dtsi | 20 wui_io82: wui0-1-2 {
21 miwus = <&miwu0 0 2>; /* GPIO82 */
31 wui_io90: wui0-2-0 {
34 wui_io91: wui0-2-1 {
37 wui_io92: wui0-2-2 {
38 miwus = <&miwu0 1 2>; /* GPIO92 */
40 wui_io93: wui0-2-3 {
43 wui_io94: wui0-2-4 {
46 wui_io95: wui0-2-5 {
49 wui_mswc: wui0-2-6 {
[all …]
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| /Zephyr-latest/boards/arm/v2m_musca_b1/ |
| D | pinmux.c | 13 #define IOMUX_MAIN_INSEL (0x68 >> 2)
14 #define IOMUX_MAIN_OUTSEL (0x70 >> 2)
15 #define IOMUX_MAIN_OENSEL (0x78 >> 2)
16 #define IOMUX_MAIN_DEFAULT_IN (0x80 >> 2)
17 #define IOMUX_ALTF1_INSEL (0x88 >> 2)
18 #define IOMUX_ALTF1_OUTSEL (0x90 >> 2)
19 #define IOMUX_ALTF1_OENSEL (0x98 >> 2)
20 #define IOMUX_ALTF1_DEFAULT_IN (0xA0 >> 2)
21 #define IOMUX_ALTF2_INSEL (0xA8 >> 2)
22 #define IOMUX_ALTF2_OUTSEL (0xB0 >> 2)
[all …]
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| /Zephyr-latest/drivers/audio/ |
| D | tas6422dac.h | 24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
31 #define MISC_CTRL_1_OTW_CONTROL_MASK (BIT_MASK(2) << 5)
35 #define MISC_CTRL_1_OTW_CONTROL_120_DEGREE 2
39 #define MISC_CTRL_1_VOLUME_RATE_MASK (BIT_MASK(2) << 2)
40 #define MISC_CTRL_1_VOLUME_RATE(val) (((val) << 2) & MISC_CTRL_1_VOLUME_RATE_MASK)
43 #define MISC_CTRL_1_VOLUME_RATE_1_STEP_EVERY_4_FSYNC 2
45 #define MISC_CTRL_1_GAIN_MASK BIT_MASK(2)
49 #define MISC_CTRL_1_GAIN_21_V_PEAK_OUTPUT 2
52 /* Miscellaneous Control 2 Register */
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| /Zephyr-latest/boards/arm/v2m_musca_s1/ |
| D | pinmux.c | 13 #define IOMUX_MAIN_INSEL (0x868 >> 2)
14 #define IOMUX_MAIN_OUTSEL (0x870 >> 2)
15 #define IOMUX_MAIN_OENSEL (0x878 >> 2)
16 #define IOMUX_MAIN_DEFAULT_IN (0x880 >> 2)
17 #define IOMUX_ALTF1_INSEL (0x888 >> 2)
18 #define IOMUX_ALTF1_OUTSEL (0x890 >> 2)
19 #define IOMUX_ALTF1_OENSEL (0x898 >> 2)
20 #define IOMUX_ALTF1_DEFAULT_IN (0x8A0 >> 2)
21 #define IOMUX_ALTF2_INSEL (0x8A8 >> 2)
22 #define IOMUX_ALTF2_OUTSEL (0x8B0 >> 2)
[all …]
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