Lines Matching full:2
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
31 #define MISC_CTRL_1_OTW_CONTROL_MASK (BIT_MASK(2) << 5)
35 #define MISC_CTRL_1_OTW_CONTROL_120_DEGREE 2
39 #define MISC_CTRL_1_VOLUME_RATE_MASK (BIT_MASK(2) << 2)
40 #define MISC_CTRL_1_VOLUME_RATE(val) (((val) << 2) & MISC_CTRL_1_VOLUME_RATE_MASK)
43 #define MISC_CTRL_1_VOLUME_RATE_1_STEP_EVERY_4_FSYNC 2
45 #define MISC_CTRL_1_GAIN_MASK BIT_MASK(2)
49 #define MISC_CTRL_1_GAIN_21_V_PEAK_OUTPUT 2
52 /* Miscellaneous Control 2 Register */
61 #define MISC_CTRL_2_SDM_OSR BIT(2)
62 #define MISC_CTRL_2_SDM_OSR_MASK BIT(2)
63 #define MISC_CTRL_2_OUTPUT_PHASE_MASK BIT_MASK(2)
66 #define MISC_CTRL_2_OUTPUT_PHASE_225_DEGREES 2
71 #define SAP_CTRL_INPUT_SAMPLING_RATE_MASK (BIT_MASK(2) << 6)
75 #define SAP_CTRL_INPUT_SAMPLING_RATE_96_KHZ 2
86 #define SAP_CTRL_INPUT_FORMAT_18_BITS_RIGHT 2
94 #define CH_STATE_CTRL_CH1_STATE_CTRL_MASK (BIT_MASK(2) << 6)
96 #define CH_STATE_CTRL_CH2_STATE_CTRL_MASK (BIT_MASK(2) << 4)
100 #define CH_STATE_CTRL_MUTE 2
103 /* Channel 1 and 2 Volume Control Registers */
122 /* DC Load Diagnostic Control 2 Register */
141 #define DC_LDG_REPORT_1_CH2_S2P BIT(2)
142 #define DC_LDG_REPORT_1_CH2_S2P_MASK BIT(2)
152 #define DC_LDG_REPORT_3_CH2_LO BIT(2)
153 #define DC_LDG_REPORT_3_CH2_LO_MASK BIT(2)
163 #define CH_FAULTS_CH2_DC BIT(2)
164 #define CH_FAULTS_CH2_DC_MASK BIT(2)
172 #define GLOBAL_FAULTS_1_VBAT_OV BIT(2)
173 #define GLOBAL_FAULTS_1_VBAT_OV_MASK BIT(2)
179 /* Global Faults 2 Register */
185 #define GLOBAL_FAULTS_2_CH2_OTSD BIT(2)
186 #define GLOBAL_FAULTS_2_CH2_OTSD_MASK BIT(2)
196 #define WARNINGS_OTW_CH2 BIT(2)
197 #define WARNINGS_OTW_CH2_MASK BIT(2)
211 #define PIN_CTRL_MASK_ILIMIT BIT(2)
212 #define PIN_CTRL_MASK_ILIMIT_MASK BIT(2)
242 #define MISC_CTRL_4_HPF_CORNER_15_HZ 2