| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77961.h | 3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
29 #define PIN_D15 RCAR_GP_PIN(0, 15)
45 #define PIN_A15 RCAR_GP_PIN(1, 15)
50 #define PIN_CS0 RCAR_GP_PIN(1, 20)
89 #define PIN_SD1_WP RCAR_GP_PIN(3, 15)
105 #define PIN_SD3_DATA6 RCAR_GP_PIN(4, 15)
123 #define PIN_HCTS0 RCAR_GP_PIN(5, 15)
[all …]
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| D | pinctrl-r8a77951.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
28 #define PIN_D15 RCAR_GP_PIN(0, 15)
44 #define PIN_A15 RCAR_GP_PIN(1, 15)
49 #define PIN_CS0 RCAR_GP_PIN(1, 20)
88 #define PIN_SD1_WP RCAR_GP_PIN(3, 15)
104 #define PIN_SD3_DATA6 RCAR_GP_PIN(4, 15)
122 #define PIN_HCTS0 RCAR_GP_PIN(5, 15)
127 #define PIN_MSIOF0_TXD RCAR_GP_PIN(5, 20)
[all …]
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| /Zephyr-latest/boards/shields/adafruit_pca9685/ |
| D | adafruit_pca9685.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "nxp,pca9685-pwm";
14 #pwm-cells = <2>;
21 compatible = "pwm-leds";
23 s_led0: s-led-0 {
24 pwms = <&pca9685_adafruit_pca9685 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
26 s_led1: s-led-1 {
27 pwms = <&pca9685_adafruit_pca9685 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
29 s_led2: s-led-2 {
30 pwms = <&pca9685_adafruit_pca9685 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
[all …]
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| /Zephyr-latest/samples/kernel/condition_variables/simple/ |
| D | README.rst | 26 .. zephyr-app-commands::
27 :zephyr-app: samples/kernel/condition_variables/simple
28 :host-os: unix
38 .. code-block:: console
55 [thread 15] working (0/5)
75 [thread 15] working (1/5)
80 [thread zephyr_app_main] done is 0 which is < 20 so waiting on cond
96 [thread 15] working (2/5)
116 [thread 15] working (3/5)
136 [thread 15] working (4/5)
[all …]
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| /Zephyr-latest/samples/userspace/shared_mem/src/ |
| D | main.h | 4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
55 #define START_WHEEL2 {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, \
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
|
| /Zephyr-latest/boards/nordic/nrf9160dk/dts/nrf52840/ |
| D | nrf9160dk_uart1_on_if0_3.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
19 <NRF_PSEL(UART_RX, 0, 20)>,
20 <NRF_PSEL(UART_RTS, 0, 15)>,
28 <NRF_PSEL(UART_RX, 0, 20)>,
29 <NRF_PSEL(UART_RTS, 0, 15)>,
31 low-power-enable;
39 pinctrl-0 = <&uart1_default_alt>;
40 pinctrl-1 = <&uart1_sleep_alt>;
41 pinctrl-names = "default", "sleep";
|
| /Zephyr-latest/tests/bluetooth/qualification/ |
| D | ICS_Zephyr_Bluetooth_Host.bqw | 1 <?xml version="1.0" encoding="utf-8"?>
2 <Qualification xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2…
5 …<Product Name="Zephyr Host" Description="host" Model="main" Website="" PublishDate="2024-11-26T00:…
12 <Feature>GAP 20/8</Feature>
35 <Feature>GAP 20/1</Feature>
36 <Feature>GAP 20A/15</Feature>
37 <Feature>GAP 20A/3</Feature>
78 <Feature>GAP 15/1</Feature>
83 <Feature>GAP 20/4</Feature>
84 <Feature>GAP 20/6</Feature>
[all …]
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| /Zephyr-latest/soc/intel/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
38 #define APL_GPIO_15 15
43 #define APL_GPIO_20 20
72 #define APL_GPIO_47 15
77 #define APL_GPIO_64 20
122 #define APL_GPIO_202 15
127 #define APL_GPIO_PMC_SPI_FS2 20
156 #define APL_GPIO_87 15
161 #define APL_GPIO_92 20
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | esp32c3-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
43 #define I2C0_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
53 #define I2C0_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
88 #define I2C0_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
98 #define I2C0_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
133 #define I2S_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT)
143 #define I2S_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT)
178 #define I2S_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2SI_SD_IN, ESP_NOSIG)
188 #define I2S_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2SI_SD_IN, ESP_NOSIG)
223 #define I2S_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT)
[all …]
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| D | esp32c6-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
59 ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
74 ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
132 ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
147 ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
189 #define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
199 #define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
238 #define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
248 #define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
287 #define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
[all …]
|
| /Zephyr-latest/samples/net/sockets/coap_client/ |
| D | README.rst | 1 .. zephyr:code-sample:: coap-client
3 :relevant-api: coap
20 .. code-block:: none
30 See the `net-tools`_ project for more details.
38 .. code-block:: console
41 15 01 01 fe 80 00 00 00 00 00 00 5c 25 e2 ff fe 15 01 01 16 33 16 33
42 00 24 3d 86 60 40 00 01 ff 54 79 70 65 3a 20 30 0a 43 6f 64 65 3a 20
43 31 0a 4d 49 44 3a 20 31 0a (76 bytes)
47 .. _`net-tools`: https://github.com/zephyrproject-rtos/net-tools
|
| /Zephyr-latest/tests/subsys/shell/shell_history/src/ |
| D | shell_history_test.c | 4 * SPDX-License-Identifier: Apache-2.0
57 * - initialize history.
58 * - put line to the history.
59 * - read line and verify that it is the one that was put.
71 z_shell_history_put(&history, exp_buf, 20); in ZTEST()
73 test_get(true, true, exp_buf, 20); in ZTEST()
87 z_shell_history_put(&history, exp_buf, 20); in ZTEST()
88 z_shell_history_put(&history, exp_buf, 20); in ZTEST()
98 * - initialize history.
99 * - put lines 1,2,3 to history.
[all …]
|
| /Zephyr-latest/boards/actinius/icarus_som_dk/ |
| D | arduino_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio0 15 0>, /* A0 */
18 <5 0 &gpio0 20 0>, /* A5 */
28 <15 0 &gpio0 31 0>, /* D9 */
33 <20 0 &gpio0 10 0>, /* SDA */
38 compatible = "arduino,uno-adc";
[all …]
|
| /Zephyr-latest/dts/bindings/gpio/ |
| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
28 https://www.microchip.com/development-tools/xplained-boards
29 …/ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_…
31 This binding provides a nexus mapping for 20 pins where pins are disposed
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
43 12 SPI(CS0) 15 16 SPI(MOSI) 13
44 14 SPI(MISO) 17 18 SPI(SCK) 15
45 GND 19 20 VDD(+3.3V)
[all …]
|
| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
17 1 3.3V 21 5V 40 GPIO 20 GND
22 6 Analog 26 Analog 35 GPIO 15 SPI MOSI
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
|
| /Zephyr-latest/drivers/pinctrl/renesas/rcar/ |
| D | pfc_r8a779f0.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
17 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
26 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
28 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
37 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
48 { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
57 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
59 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
70 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
[all …]
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| D | pfc_r8a77951.c | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
16 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
27 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
38 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
49 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
60 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
71 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
82 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
[all …]
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| D | pfc_r8a77961.c | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
16 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
27 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
38 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
49 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
60 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
71 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
82 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
[all …]
|
| /Zephyr-latest/boards/shields/waveshare_epaper/ |
| D | waveshare_epaper_gdeh0213b72.overlay | 4 * SPDX-License-Identifier: Apache-2.0
15 compatible = "zephyr,mipi-dbi-spi";
16 spi-dev = <&arduino_spi>;
17 dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
18 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
19 #address-cells = <1>;
20 #size-cells = <0>;
24 mipi-max-frequency = <4000000>;
28 busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
31 gdv = [15];
[all …]
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| /Zephyr-latest/boards/adafruit/nrf52_adafruit_feather/ |
| D | feather_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "adafruit-feather-header";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio0 2 0>, /* A0 */
24 <11 0 &gpio0 20 0>, /* PIN_DFU */
28 <15 0 &gpio0 30 0>, /* A6 */
32 <19 0 &gpio0 15 0>, /* P0.15 */
33 <20 0 &gpio0 16 0>; /* P0.16 */
|
| /Zephyr-latest/boards/panasonic/pan1783/ |
| D | pan1783_nrf5340_cpunet-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
9 psels = <NRF_PSEL(UART_TX, 0, 20)>,
15 bias-pull-up;
21 psels = <NRF_PSEL(UART_TX, 0, 20)>,
25 low-power-enable;
40 low-power-enable;
46 psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
54 psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
57 low-power-enable;
|
| /Zephyr-latest/include/zephyr/dt-bindings/memory-attr/ |
| D | memory-attr.h | 4 * SPDX-License-Identifier: Apache-2.0
16 #define DT_MEM_ATTR_MASK GENMASK(15, 0)
21 #define DT_MEM_NON_VOLATILE BIT(1) /* non-volatile */
22 #define DT_MEM_OOO BIT(2) /* out-of-order */
23 #define DT_MEM_DMA BIT(3) /* DMA-able */
24 #define DT_MEM_UNKNOWN BIT(15) /* must be last */
44 * See for example `include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h`
46 #define DT_MEM_ARCH_ATTR_MASK GENMASK(31, 20)
48 #define DT_MEM_ARCH_ATTR_SHIFT (20)
|
| /Zephyr-latest/boards/96boards/nitrogen/ |
| D | 96b_nitrogen-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
10 <NRF_PSEL(UART_RX, 0, 15)>,
19 <NRF_PSEL(UART_RX, 0, 15)>,
22 low-power-enable;
28 psels = <NRF_PSEL(TWIM_SDA, 0, 20)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 20)>,
37 low-power-enable;
54 low-power-enable;
|
| /Zephyr-latest/include/zephyr/dt-bindings/reset/ |
| D | npcx7_reset.h | 4 * SPDX-License-Identifier: Apache-2.0
29 #define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
33 #define NPCX_RESET_ITIM16_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
58 #define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
63 #define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
84 #define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
86 #define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
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