| /Zephyr-latest/dts/bindings/gpio/ |
| D | arduino-mkr-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 * One side of the 14-pin header is analog inputs and digital signals.
10 A1 to A6 is Analog input. The outside pin is AREF.
11 A0 that is next to AREF used as a DAC output pin too.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
18 through 14 correspond to D0 through D21, and parent pins 15 through 21
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
[all …]
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| D | arduino-nano-header-r3.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 * A 15-pin header with mostly digital signals. The additional NRST (pin3)
10 and GND (pin 4) pins are not exposed by this binding.
11 * A 15-pin Analog Input and power supply header. This has analog input
16 through 13 correspond to D0 through D13, and parent pins 14 through 21
19 1 D1 VIN -
20 0 D0 GND -
21 - RESET RESET -
22 - GND 5V -
30 9 D9 A0/D14 14
[all …]
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| D | nxp,lcd-8080.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,lcd-8080"
8 GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel).
9 These pins are exposed on a 32 pin connector. The pins have the
12 Pin Number Usage
24 12 LCD 8080 interface D/C pin
25 13 LCD 8080 interface CS pin
26 14 LCD 8080 interface WR pin
27 15 LCD 8080 interface RD pin
28 16 LCD TE(tearing effect) pin
[all …]
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| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
42 10 UART(RX) 13 14 UART(TX) 11
44 14 SPI(MISO) 17 18 SPI(SCK) 15
[all …]
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| D | quicklogic,eos-s3-gpio.yaml | 3 compatible: "quicklogic,eos-s3-gpio"
5 include: [gpio-controller.yaml, base.yaml]
11 "#gpio-cells":
14 pin-secondary-config:
19 a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
25 "3 : 14 / 30"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
32 "pin-secondary-config = <0x04>;"
34 gpio-cells:
35 - pin
[all …]
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| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
[all …]
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| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
23 7 SPI CLK 27 Analog 34 GPIO 14 SPI MISO
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
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| D | sparkfun,micromod-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
[all …]
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| D | nxp,parallel-lcd-connector.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,parallel-lcd-connector"
9 exposed on a 40 pin flexible printed cable connector. The pins have the
12 FPC Pin Function
17 5-7 GND
18 8-12 LCD D11-D15
19 13-14 GND
20 15-20 LCD D5-D10
21 21-23 GND
22 24-28 LCD D0-D4
[all …]
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| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
[all …]
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| /Zephyr-latest/dts/x86/intel/ |
| D | elkhart_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
[all …]
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| D | raptor_lake_p.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
[all …]
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| D | raptor_lake_s.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
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| D | apollo_lake.dtsi | 2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
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| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | udoo_neo_full_mcimx6x_m4.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 out-gpios = <&gpio5 14 0>; /* J4 pin 4 */
11 in-gpios = <&gpio5 15 0>; /* J4 pin 3 */
|
| /Zephyr-latest/soc/xlnx/zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
122 #define MIO14 14
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
186 #define MIO_GROUP_SPI1_0_SS1_PINS 14
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
219 #define MIO_GROUP_CAN0_1_GRP_PINS 14, 15
[all …]
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| /Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/ |
| D | nucleo_f091rc.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
8 * i2c2 PA12 CN10:12 PA11 CN10:14
10 * Short Pin PB9 to PA12, and PB8 to PA11, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
23 /* i2c2 is disabled by default because of pin conflict with can1 */
26 compatible = "zephyr,i2c-target-eeprom";
|
| D | nucleo_g071rb.overlay | 3 * SPDX-License-Identifier: Apache-2.0
9 * Pin Hdr Pin Hdr
11 * i2c2 PA12 CN10:12 PA11 CN10:14
13 * Short Pin PB9 to PA12, and PB8 to PA11, for the test to pass.
18 compatible = "zephyr,i2c-target-eeprom";
26 compatible = "zephyr,i2c-target-eeprom";
|
| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/src/ |
| D | main.c | 5 * SPDX-License-Identifier: Apache-2.0
25 * Configure pin mux. in board_setup()
31 printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15); in board_setup()
35 if (PIN_OUT != 14) { in board_setup()
36 printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14); in board_setup()
40 /* Configure pin RGMII2_RD2 as GPIO5_IO14. */ in board_setup()
50 /* Configure pin RGMII2_RD3 as GPIO5_IO15. */ in board_setup()
71 /* This functions allows to programmatically short-circuit SOC GPIO pins */ in board_setup()
|
| /Zephyr-latest/dts/bindings/stepper/ti/ |
| D | ti,drv8424.yaml | 1 # SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
2 # SPDX-License-Identifier: Apache-2.0
10 The step gpio pin needs to be connected directly to the SOC GPIO controller, connecting the
11 pin to a controller connected via a bus such as i2c or others will lead to undefined behaviour.
18 dir-gpios = <&arduino_header 18 0>;
19 step-gpios = <&arduino_header 19 0>;
20 sleep-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
21 en-gpios = <&arduino_header 14 0>;
22 m0-gpios = <&mikroe_stepper_gpios 0 0>;
23 m1-gpios = <&mikroe_stepper_gpios 1 0>;
[all …]
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| /Zephyr-latest/dts/bindings/lora/ |
| D | st,stm32wl-subghz-radio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32wl-subghz-radio"
8 include: semtech,sx126x-base.yaml
16 power-amplifier-output:
20 Selects between the low- and high-power power amplifier output pin.
22 - "rfo-lp"
23 - "rfo-hp"
25 rfo-lp-max-power:
27 default: 14
31 The default setting of +14 dBm is a prevalent board configuration;
[all …]
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| /Zephyr-latest/soc/microchip/mec/common/ |
| D | soc_i2c.h | 3 * SPDX-License-Identifier: Apache-2.0
14 /* 144-pin package I2C port masks */
35 #define MCHP_I2C_PORT_14 14
40 * Read pin states of specified I2C port.
42 * lines b[0]=SCL pin state at pad, b[1]=SDA pin state at pad
43 * Returns 0 success or -EINVAL if port is not support or lines is NULL.
|
| /Zephyr-latest/soc/ti/simplelink/cc13x2x7_cc26x2x7/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
26 Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1).
45 associated pin is at the correct logic level on reset.
48 int "ROM bootloader backdoor pin"
53 Set the pin that is level checked if the bootloader backdoor is
62 Set the active level of the pin selected for the bootloader backdoor.
|
| /Zephyr-latest/boards/st/nucleo_h503rb/ |
| D | st_morpho_connector.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
7 #include <zephyr/dt-bindings/gpio/st-morpho-header.h>
10 st_morpho_header: st-morpho-header {
11 compatible = "st-morpho-header";
12 #gpio-cells = <2>;
13 gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
14 gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
15 gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
23 <ST_MORPHO_L_15 0 &gpioa 14 0>,
[all …]
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| /Zephyr-latest/soc/ti/simplelink/cc13x2_cc26x2/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
25 Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1).
44 associated pin is at the correct logic level on reset.
47 int "ROM bootloader backdoor pin"
52 Set the pin that is level checked if the bootloader backdoor is
61 Set the active level of the pin selected for the bootloader backdoor.
|
