| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,ina219.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
16 Current LSB = max expected current [A] / 2^15
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77961.h | 3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
26 #define PIN_D12 RCAR_GP_PIN(0, 12)
29 #define PIN_D15 RCAR_GP_PIN(0, 15)
42 #define PIN_A12 RCAR_GP_PIN(1, 12)
45 #define PIN_A15 RCAR_GP_PIN(1, 15)
71 #define PIN_AVB_LINK RCAR_GP_PIN(2, 12)
86 #define PIN_SD0_CD RCAR_GP_PIN(3, 12)
[all …]
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| D | pinctrl-r8a77951.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
25 #define PIN_D12 RCAR_GP_PIN(0, 12)
28 #define PIN_D15 RCAR_GP_PIN(0, 15)
41 #define PIN_A12 RCAR_GP_PIN(1, 12)
44 #define PIN_A15 RCAR_GP_PIN(1, 15)
70 #define PIN_AVB_LINK RCAR_GP_PIN(2, 12)
85 #define PIN_SD0_CD RCAR_GP_PIN(3, 12)
88 #define PIN_SD1_WP RCAR_GP_PIN(3, 15)
[all …]
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| /Zephyr-latest/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
44 IPC_EVENT_BIT(12) | \
47 IPC_EVENT_BIT(15) \
64 [12] = BIT(12),
67 [15] = BIT(15),
82 [12] = BIT(12),
85 [15] = BIT(15),
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| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | sam4s_xplained.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc0 5>, <&adc0 15>;
15 #address-cells = <1>;
16 #size-cells = <0>;
23 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
24 zephyr,input-positive = <5>;
25 zephyr,resolution = <12>;
30 reg = <15>;
33 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
34 zephyr,input-positive = <15>;
[all …]
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| /Zephyr-latest/dts/bindings/display/ |
| D | led-strip-matrix.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "led-strip-matrix"
9 include: display-controller.yaml
24 [12][13][14][15]
30 [15][14][13][12]
32 start-from-right:
41 [12][13][14][15]
47 [15][14][13][12]
49 start-from-bottom:
55 [12][13][14][15]
[all …]
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| /Zephyr-latest/samples/tfm_integration/tfm_secure_partition/dummy_partition/ |
| D | dummy_partition.c | 4 * SPDX-License-Identifier: Apache-2.0
21 { {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
22 { {1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
23 { {2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
24 { {3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
25 { {4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
77 if (msg->in_size[0] != sizeof(secret_index)) { in tfm_dp_secret_digest_ipc()
82 num = psa_read(msg->handle, 0, &secret_index, msg->in_size[0]); in tfm_dp_secret_digest_ipc()
83 if (num != msg->in_size[0]) { in tfm_dp_secret_digest_ipc()
87 return tfm_dp_secret_digest(secret_index, msg->out_size[0], in tfm_dp_secret_digest_ipc()
[all …]
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| /Zephyr-latest/boards/st/nucleo_h533re/ |
| D | st_morpho_connector.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
7 #include <zephyr/dt-bindings/gpio/st-morpho-header.h>
10 st_morpho_header: st-morpho-header {
11 compatible = "st-morpho-header";
12 #gpio-cells = <2>;
13 gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
14 gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
15 gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
17 <ST_MORPHO_L_3 0 &gpioc 12 0>,
[all …]
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| /Zephyr-latest/tests/lib/c_lib/common/src/ |
| D | test_qsort.c | 4 * SPDX-License-Identifier: Apache-2.0
17 return (aa > bb) - (aa < bb); in compare_ints()
33 "out-of-bounds modifications detected"); in ZTEST()
46 int actual_int[] = { 42, -42 }; in ZTEST()
47 const int expect_int[] = { -42, 42 }; in ZTEST()
55 int actual_int[] = { 42, -42, 0 }; in ZTEST()
56 const int expect_int[] = { -42, 0, 42 }; in ZTEST()
64 int actual_int[] = { 42, -42, 0, -42 }; in ZTEST()
65 const int expect_int[] = { -42, -42, 0, 42 }; in ZTEST()
74 * NUMS="$(for i in `seq 0 63`; do echo -n "$(((RANDOM - 16384) % 100)), "; done)" in ZTEST()
[all …]
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| /Zephyr-latest/soc/intel/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
35 #define APL_GPIO_12 12
38 #define APL_GPIO_15 15
69 #define APL_GPIO_44 12
72 #define APL_GPIO_47 15
103 #define APL_GPIO_SVOD0_DATA 12
119 #define APL_GPIO_199 12
122 #define APL_GPIO_202 15
153 #define APL_GPIO_84 12
[all …]
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| /Zephyr-latest/boards/shields/wnc_m14a2a/boards/ |
| D | nrf52840dk_nrf52840.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 <NRF_PSEL(UART_RTS, 1, 12)>,
13 <NRF_PSEL(UART_CTS, 1, 15)>;
21 <NRF_PSEL(UART_RTS, 1, 12)>,
22 <NRF_PSEL(UART_CTS, 1, 15)>;
23 low-power-enable;
29 * WNC-M14A2A shield uses an odd UART available on *some* Arduino-R3-compatible
33 current-speed = <115200>;
34 hw-flow-control;
37 pinctrl-0 = <&uart1_default_alt>;
[all …]
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| /Zephyr-latest/dts/bindings/power/ |
| D | nxp,s32-mc-rgm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,s32-mc-rgm"
14 func-reset-threshold:
16 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
17 default: 15
26 dest-reset-threshold:
28 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
34 resets which keeps the chip in the reset state until the next power-on
|
| /Zephyr-latest/tests/drivers/adc/adc_api/boards/ |
| D | nucleo_h753zi.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc1 12>, <&adc1 15>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 reg = <12>;
22 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
27 reg = <15>;
30 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
|
| D | nucleo_h7a3zi_q.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc1 12>, <&adc1 15>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 reg = <12>;
22 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
27 reg = <15>;
30 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
|
| D | b_u585i_iot02a.overlay | 2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc1 15>, <&adc1 16>;
16 dma-names = "gpdma";
18 pinctrl-0 = <&adc1_in15_pb0 &adc1_in16_pb1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 reg = <15>;
26 zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
27 zephyr,resolution = <12>;
34 zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
[all …]
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| D | sam4s_xplained.overlay | 2 * SPDX-License-Identifier: Apache-2.0
9 io-channels = <&adc0 15>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 reg = <15>;
22 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
23 zephyr,resolution = <12>;
24 zephyr,input-positive = <15>;
|
| /Zephyr-latest/boards/st/nucleo_h563zi/ |
| D | st_morpho_connector.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
7 #include <zephyr/dt-bindings/gpio/st-morpho-header.h>
10 st_morpho_header: st-morpho-header {
11 compatible = "st-morpho-header";
12 #gpio-cells = <2>;
13 gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
14 gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
15 gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
17 <ST_MORPHO_L_3 0 &gpioc 12 0>,
[all …]
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| /Zephyr-latest/samples/userspace/shared_mem/src/ |
| D | main.h | 4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
55 #define START_WHEEL2 {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, \
57 #define REFLECT {1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, \
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
|
| /Zephyr-latest/dts/arm/microchip/ |
| D | mec172x_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
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| /Zephyr-latest/drivers/adc/ |
| D | Kconfig.mcux | 4 # SPDX-License-Identifier: Apache-2.0
23 bool "MCUX 12B1MSPS SAR ADC driver"
28 Enable the MCUX 12B1MSPS SAR ADC driver.
116 default 15
117 range 1 15
121 15 ADC channels. This value corresponds to how many of the CMD
|
| /Zephyr-latest/boards/st/stm32h7s78_dk/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioc 0 0>, /* A0 */
16 <3 0 &gpiof 12 0>, /* A3 */
22 <9 0 &gpiod 12 0>, /* D3 */
25 <12 0 &gpiod 15 0>, /* D6 */
28 <15 0 &gpiof 6 0>, /* D9 */
[all …]
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| /Zephyr-latest/boards/st/stm32mp157c_dk2/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpiof 14 0>, /* A0 */
18 <5 0 &gpiof 12 0>, /* A5 */
24 <11 0 &gpiod 15 0>, /* D5 */
25 <12 0 &gpioe 9 0>, /* D6 */
28 <15 0 &gpioh 6 0>, /* D9 */
[all …]
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| /Zephyr-latest/boards/nordic/nrf9160dk/ |
| D | nrf9160dk_nrf52840_0_14_0.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 board-control {
9 nrf_interface_pin_9_routing: switch-nrf-if9-ctrl {
10 compatible = "nordic,nrf9160dk-optional-routing";
11 control-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
15 io_expander_pins_routing: switch-io-exp-en {
16 compatible = "nordic,nrf9160dk-optional-routing";
17 control-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
21 external_flash_pins_routing: switch-ext-mem-ctrl {
22 compatible = "nordic,nrf9160dk-optional-routing";
[all …]
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| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | nxp,s32-siul2-eirq.yaml | 1 # Copyright 2022-2024 NXP
3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nxp,s32-siul2-eirq"
9 include: [interrupt-controller.yaml, pinctrl-device.yaml, base.yaml]
15 pinctrl-0:
18 pinctrl-names:
21 filter-prescaler:
23 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
31 * IFCP is 0 to 15.
33 child-binding:
[all …]
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