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/Zephyr-Core-3.5.0/dts/bindings/ethernet/
Dethernet-phy.yaml1 # Copyright (c) 2021 IP-Logix Inc.
2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "ethernet-phy"
16 no-reset:
19 fixed-link:
23 - "10BASE-T Half-Duplex"
24 - "10BASE-T Full-Duplex"
25 - "100BASE-T Half-Duplex"
26 - "100BASE-T Full-Duplex"
Dmicrochip,enc424j600.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ENC424J600 standalone 100BASE-T Ethernet controller with SPI interface
9 include: [spi-device.yaml, ethernet-controller.yaml]
12 int-gpios:
13 type: phandle-array
Dwiznet,w5500.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: W5500 standalone 10/100BASE-T Ethernet controller with SPI interface
8 include: [spi-device.yaml, ethernet-controller.yaml]
11 int-gpios:
12 type: phandle-array
19 reset-gpios:
20 type: phandle-array
/Zephyr-Core-3.5.0/include/zephyr/net/
Dmii.h5 * SPDX-License-Identifier: Apache-2.0
31 /** Auto-Negotiation Advertisement Register */
33 /** Auto-Negotiation Link Partner Ability Reg */
35 /** Auto-Negotiation Expansion Register */
37 /** Auto-Negotiation Next Page Transmit Register */
39 /** Auto-Negotiation Link Partner Received Next Page Reg */
41 /** 1000BASE-T Control Register */
43 /** 1000BASE-T Status Register */
57 /** 10=1000Mbps 01=100Mbps; 00=10Mbps */
59 /** Auto-Negotiation enable */
[all …]
Dphy.h8 * Copyright (c) 2021 IP-Logix Inc.
11 * SPDX-License-Identifier: Apache-2.0
31 /** 10Base-T Half-Duplex */
33 /** 10Base-T Full-Duplex */
35 /** 100Base-T Half-Duplex */
37 /** 100Base-T Full-Duplex */
39 /** 1000Base-T Half-Duplex */
41 /** 1000Base-T Full-Duplex */
110 * @retval -EIO If communication with PHY failed.
111 * @retval -ENOTSUP If not supported.
[all …]
/Zephyr-Core-3.5.0/drivers/ethernet/
Dphy_cyclonev.c4 * SPDX-License-Identifier: Apache-2.0
8 * downloads/en/DeviceDoc/KSZ9021RL-RN-Data-Sheet-DS00003050A.pdf)
51 #define PHY_AUTOCAP BIT(3) /* Auto-negotiation capability */
55 /* Auto-Negotiation Advertisement */
64 /* 1000Base-T Control */
103 return -1; in alt_eth_phy_write_register()
122 sys_write32(phy_value & 0xffff, EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); in alt_eth_phy_write_register()
124 sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
130 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
135 return -1; in alt_eth_phy_write_register()
[all …]
Dphy_gecko.c5 * SPDX-License-Identifier: Apache-2.0
18 /* Maximum time to establish a link through auto-negotiation for
19 * 10BASE-T, 100BASE-TX is 3.7s, to add an extra margin the timeout
27 eth->NETWORKCTRL |= ETH_NETWORKCTRL_MANPORTEN; in mdio_bus_enable()
33 eth->NETWORKCTRL &= ~ETH_NETWORKCTRL_MANPORTEN; in mdio_bus_disable()
39 uint32_t retries = 100U; /* will wait up to 1 s */ in mdio_bus_wait()
41 while (!(eth->NETWORKSTATUS & ETH_NETWORKSTATUS_MANDONE)) { in mdio_bus_wait()
42 if (retries-- == 0U) { in mdio_bus_wait()
44 return -ETIMEDOUT; in mdio_bus_wait()
60 eth->PHYMNGMNT = ETH_PHYMNGMNT_WRITE0_DEFAULT in mdio_bus_send()
[all …]
Dphy_xlnx_gem.c6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
31 * @param base_addr Base address of the GEM's register space
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
54 k_busy_wait(100); in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
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/Zephyr-Core-3.5.0/samples/drivers/led_xec/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
17 #define K_WAIT_DELAY 100u
70 uint32_t base = led_dev_table[n].base_addr; in led_test() local
72 LOG_INF("BBLED instance %d @ %x", n, base); in led_test()
73 print_bbled_regs(base); in led_test()
76 LOG_ERR("%s: device not ready", dev->name); in led_test()
80 LOG_INF("blink: T = 0.5 second, duty cycle = 0.5"); in led_test()
87 print_bbled_regs(base); in led_test()
92 LOG_INF("blink: T = 3 seconds, duty cycle = 0.4"); in led_test()
99 print_bbled_regs(base); in led_test()
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/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_rt1010.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 clock-frequency = <500000000>;
26 /delete-node/ arm-podf;
28 ipg-podf {
29 clock-div = <4>;
51 dma-channels = <16>;
56 /* Remove GPIO3-GPIO9, they don't exist on RT1010 */
57 /delete-node/ gpio@401c0000;
58 /delete-node/ gpio@401c4000;
59 /delete-node/ gpio@42000000;
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/Zephyr-Core-3.5.0/samples/net/cloud/tagoio_http_post/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
26 LOG_DBG("Partial data received (%zd bytes)", rsp->data_len); in response_cb()
28 LOG_DBG("All the data received (%zd bytes)", rsp->data_len); in response_cb()
31 LOG_DBG("Response status %s", rsp->http_status); in response_cb()
38 #define base 1000.00f in collect_data() macro
42 /* Generate a temperature between 20 and 100 celsius degree */ in collect_data()
43 temp = ((sys_rand32_get() % (upper - lower + 1)) + lower); in collect_data()
44 temp /= base; in collect_data()
51 /* LOG doesn't print float #18351 */ in collect_data()
77 LOG_INF("TagoIO IoT - HTTP Client - Temperature demo"); in main()
/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_mcux.c4 * SPDX-License-Identifier: Apache-2.0
23 #include "i2c-priv.h"
26 ((I2C_Type *)((const struct i2c_mcux_config * const)(dev)->config)->base)
29 I2C_Type *base; member
54 I2C_Type *base = DEV_BASE(dev); in i2c_mcux_configure() local
55 struct i2c_mcux_data *data = dev->data; in i2c_mcux_configure()
56 const struct i2c_mcux_config *config = dev->config; in i2c_mcux_configure()
61 return -EINVAL; in i2c_mcux_configure()
65 return -EINVAL; in i2c_mcux_configure()
70 baudrate = KHZ(100); in i2c_mcux_configure()
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Di2c_rv32m1_lpi2c.c8 * SPDX-License-Identifier: Apache-2.0
22 #include "i2c-priv.h"
25 LPI2C_Type *base; member
45 const struct rv32m1_lpi2c_config *config = dev->config; in rv32m1_lpi2c_configure()
51 /* Slave mode not supported - yet */ in rv32m1_lpi2c_configure()
53 return -ENOTSUP; in rv32m1_lpi2c_configure()
57 /* FSL LPI2C driver only supports 7-bit addressing */ in rv32m1_lpi2c_configure()
59 return -ENOTSUP; in rv32m1_lpi2c_configure()
64 baudrate = KHZ(100); in rv32m1_lpi2c_configure()
72 /* TODO: only if SCL pin implements current source pull-up */ in rv32m1_lpi2c_configure()
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Di2c_mcux_flexcomm.c5 * SPDX-License-Identifier: Apache-2.0
20 #include "i2c-priv.h"
23 I2C_Type *base; member
49 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_configure()
50 struct mcux_flexcomm_data *data = dev->data; in mcux_flexcomm_configure()
51 I2C_Type *base = config->base; in mcux_flexcomm_configure() local
56 return -EINVAL; in mcux_flexcomm_configure()
60 return -EINVAL; in mcux_flexcomm_configure()
65 baudrate = KHZ(100); in mcux_flexcomm_configure()
74 return -EINVAL; in mcux_flexcomm_configure()
[all …]
Di2c_xilinx_axi.c1 /* SPDX-License-Identifier: Apache-2.0 */
17 #include "i2c-priv.h"
21 mem_addr_t base; member
50 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_target_register()
51 struct i2c_xilinx_axi_data *data = dev->data; in i2c_xilinx_axi_target_register()
57 if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) { in i2c_xilinx_axi_target_register()
59 return -EOPNOTSUPP; in i2c_xilinx_axi_target_register()
62 k_mutex_lock(&data->mutex, K_FOREVER); in i2c_xilinx_axi_target_register()
63 key = k_spin_lock(&data->lock); in i2c_xilinx_axi_target_register()
65 if (data->target_cfg) { in i2c_xilinx_axi_target_register()
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Di2c_mcux_lpi2c.c3 * Copyright 2019-2023, NXP
6 * SPDX-License-Identifier: Apache-2.0
29 #include "i2c-priv.h"
36 LPI2C_Type *base; member
67 const struct mcux_lpi2c_config *config = dev->config; in mcux_lpi2c_configure()
68 struct mcux_lpi2c_data *data = dev->data; in mcux_lpi2c_configure()
69 LPI2C_Type *base = config->base; in mcux_lpi2c_configure() local
75 return -EINVAL; in mcux_lpi2c_configure()
79 return -EINVAL; in mcux_lpi2c_configure()
84 baudrate = KHZ(100); in mcux_lpi2c_configure()
[all …]
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h>
23 #define PWM_CTRX_MIN 100
38 /* PWM prescaler control register base */
39 struct pwm_it8xxx2_regs *base; member
48 const struct pwm_it8xxx2_cfg *config = dev->config; in pwm_enable()
49 volatile uint8_t *reg_pcsgr = (uint8_t *)config->reg_pcsgr; in pwm_enable()
50 int ch = config->channel; in pwm_enable()
68 * 1) pwm_set_cycles_usec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles() in pwm_it8xxx2_get_cycles_per_sec()
72 * 2) pwm_set_cycles_nsec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles() in pwm_it8xxx2_get_cycles_per_sec()
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/Zephyr-Core-3.5.0/doc/project/
Drelease_process.rst6 The Zephyr project releases on a time-based cycle, rather than a feature-driven
10 A time-based release process enables the Zephyr project to provide users with a
12 roughly 4-month release cycle allows the project to coordinate development of
19 - Release tagging procedure:
21 - linear mode on main branch,
22 - release branches for maintenance after release tagging.
23 - Each release period will consist of a development phase followed by a
29 - Development phase: all changes are considered and merged, subject to
31 - Stabilisation phase: the release manager creates a vN-rc1 tag and the tree
33 - CI sees the tag, builds and runs tests; Test teams analyse the report from the
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/Zephyr-Core-3.5.0/drivers/i3c/
Di3c_mcux.c6 * SPDX-License-Identifier: Apache-2.0
71 I3C_Type *base; member
102 * I3C Push-pull mode.
146 * @param reg Pointer to 32-bit Register.
156 * @retval -ETIMEDOUT Exhausted all delays without matching.
164 int ret = -ETIMEDOUT; in reg32_poll_timeout()
186 * @param reg Pointer to 32-bit Register.
204 * @param reg Pointer to 32-bit register.
221 * @param reg Pointer to 32-bit register.
234 * @param base Pointer to controller registers.
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/Zephyr-Core-3.5.0/doc/kernel/services/synchronization/
Dmutexes.rst45 When the mutex becomes unlocked it is then locked by the highest-priority
78 The owning thread's base priority is saved in the mutex when it obtains the
82 base priority from the value saved in the mutex.
85 involved. However, if multiple mutexes are involved, sub-optimal behavior will
102 .. code-block:: c
113 .. code-block:: c
125 .. code-block:: c
129 The following code waits up to 100 milliseconds for the mutex to become
132 .. code-block:: c
134 if (k_mutex_lock(&my_mutex, K_MSEC(100)) == 0) {
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/Zephyr-Core-3.5.0/drivers/dai/intel/dmic/
Ddmic.c4 * SPDX-License-Identifier: Apache-2.0
27 /* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
33 /* Helper macro to read 64-bit data using two 32-bit data read */
40 * fairly accurately exponent for x in range -2.0 .. +2.0. The iteration
61 p = num * x; /* Q9.23 x Q3.29 -> Q12.52 */ in exp_small_fixed()
79 if (x < Q_CONVERT_FLOAT(-11.5, 27)) in exp_fixed()
107 if (db < Q_CONVERT_FLOAT(-100.0, 24)) in db2lin_fixed()
118 uint32_t dest = dmic->reg_base + reg; in dai_dmic_update_bits()
120 LOG_INF("%s base %x, reg %x, mask %x, value %x", __func__, in dai_dmic_update_bits()
121 dmic->reg_base, reg, mask, val); in dai_dmic_update_bits()
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/Zephyr-Core-3.5.0/boards/arm/mr_canhubk3/doc/
Dindex.rst3 NXP MR-CANHUBK3
9 `NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such
11 features an `NXP S32K344`_ general-purpose automotive microcontroller based on
12 an Arm Cortex-M7 core (Lock-Step).
16 :alt: NXP MR-CANHUBK3 (TOP)
21 - NXP S32K344
22 - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.)
23 - 4 MB of program flash, with ECC
24 - 320 KB RAM, with ECC
25 - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI
[all …]
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_npcx.c4 * SPDX-License-Identifier: Apache-2.0
18 * +---------------------+ +-----------------+
19 * LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
21 * +---------------------+ | +-----------------+
22 * +---------------------------------+
24 * | +-------------------+ +-----------------+
25 * +--->| Watchdog Prescale |--->| 8-Bit Watchdog |-----> Watchdog Event/Reset
27 * +-------------------+ +-----------------+
49 * Maximum watchdog window time. Since the watchdog counter is 8-bits, maximum
58 #define NPCX_WDT_MIN_WND_TIME 100UL
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/Zephyr-Core-3.5.0/boards/arm/fvp_baser_aemv8r_aarch32/doc/
Dindex.rst3 Arm FVP BaseR AEMv8-R AArch32
9 This board configuration uses Armv8-R AEM FVP [1]_ to emulate a generic
10 Armv8-R [2]_ 32-bit hardware platform.
17 The Armv8-R AEM FVP is a free of charge Armv8-R Fixed Virtual Platform. It
18 supports the latest Armv8-R feature set. Please refer to FVP documentation
21 To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
33 +-----------------------+------------+----------------------+
36 | GICv3 | on-chip | interrupt controller |
37 +-----------------------+------------+----------------------+
38 | PL011 UART | on-chip | serial port |
[all …]
/Zephyr-Core-3.5.0/subsys/shell/modules/
Dkernel_service.c5 * SPDX-License-Identifier: Apache-2.0
68 if (strcmp("-p", argv[1]) && strcmp("--pretty", argv[1]) != 0) { in cmd_kernel_uptime()
70 return -EIO; in cmd_kernel_uptime()
107 size_t size = thread->stack_info.size; in shell_tdata_dump()
119 shell_print(sh, "%s%p %-10s", in shell_tdata_dump()
125 thread->base.user_options, in shell_tdata_dump()
126 thread->base.prio, in shell_tdata_dump()
127 (int64_t)thread->base.timeout.dticks); in shell_tdata_dump()
130 thread->entry.pEntry); in shell_tdata_dump()
144 pcnt = (rt_stats_thread.execution_cycles * 100U) / in shell_tdata_dump()
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