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/nrf_hw_models-3.6.0/src/HW_models/
DNHW_config.h23 #define NHW_HAS_PPI 1
25 #define NHW_USE_MDK_TYPES 1 /* The HW registers layout types are taken from the MDK */
27 #define NHW_AAR_TOTAL_INST 1
32 #define NHW_CCM_TOTAL_INST 1
36 #define NHW_CLKPWR_TOTAL_INST 1
40 #define NHW_CLKPWR_HAS_CALTIMER 1
46 #define NHW_ECB_TOTAL_INST 1
53 #define NHW_EGU_1 1
67 #define NHW_GPIOTE_TOTAL_INST 1
71 #define NHW_INTCTRL_TOTAL_INST 1
[all …]
DNHW_RADIO_timings.c24 /* The versions are [1,2Mbps, 15.4] [Normal, Fast] [No_TIFS, HW_TIFS] */
31 /*Indexed as 1Mbps, 2Mbps, 15.4*/
41 /* The versions are [1, 2Mbps, 15.4] [Normal, Fast] [No_TIFS, HW_TIFS] */ in nrfra_timings_init()
43 radio_timings.TX_RU_time[0][1][0] = 41; // 41000 in nrfra_timings_init()
44 radio_timings.TX_RU_time[0][0][1] = 141; //141000 in nrfra_timings_init()
46 radio_timings.TX_RU_time[1][1][0] = 40; // 40000 in nrfra_timings_init()
47 radio_timings.TX_RU_time[1][0][1] = 140; //140000 in nrfra_timings_init()
48 radio_timings.TX_RU_time[1][0][0] = 129; //128900 in nrfra_timings_init()
49 radio_timings.TX_RU_time[2][1][0] = 40; // 40000 in nrfra_timings_init()
50 radio_timings.TX_RU_time[2][0][1] = 130; //130000 - Is this correct? or should it be 169us? in nrfra_timings_init()
[all …]
DNRF_PPI.c56 void nrf_ppi_TASK_CHG1_EN(void) { nrf_ppi_TASK_CHG_ENDIS(1,true); } in nrf_ppi_TASK_CHG1_EN()
62 void nrf_ppi_TASK_CHG1_DIS(void) { nrf_ppi_TASK_CHG_ENDIS(1,false); } in nrf_ppi_TASK_CHG1_DIS()
125 { (void*)&NRF_UARTE_regs[1].TASKS_STARTRX, nhw_uarte1_TASKS_STARTRX},
126 { (void*)&NRF_UARTE_regs[1].TASKS_STOPRX, nhw_uarte1_TASKS_STOPRX},
127 { (void*)&NRF_UARTE_regs[1].TASKS_STARTTX, nhw_uarte1_TASKS_STARTTX},
128 { (void*)&NRF_UARTE_regs[1].TASKS_STOPTX, nhw_uarte1_TASKS_STOPTX},
129 { (void*)&((NRF_UART_Type *)&NRF_UARTE_regs[1])->TASKS_SUSPEND, nhw_uarte1_TASKS_SUSPEND},
130 { (void*)&NRF_UARTE_regs[1].TASKS_FLUSHRX, nhw_uarte1_TASKS_FLUSHRX},
140 { (void*)&NRF_GPIOTE_regs.TASKS_OUT[1], nrf_gpiote_TASKS_OUT_1},
148 { (void*)&NRF_GPIOTE_regs.TASKS_SET[1], nrf_gpiote_TASKS_SET_1},
[all …]
DNRF5340_peri_types.h89 … /*!< (@ 0x00000010) Sample count for ring oscillator 1 …
254 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
262 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
271 #define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
284 #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
297 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
306 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
315 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
324 #define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
337 #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
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DNRF_GPIO.c12 * * Note a.1:
24 * * Note b.1:
60 static uint32_t INPUT_mask[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].INPUT (0: enabled; 1: disable…
61 static uint32_t SENSE_mask[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].SENSE.en (1: enabled; 0: disa…
62 static uint32_t SENSE_inv[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].SENSE.inv (1: inverted;0: not…
65 * Is the output driven by another peripheral (1) or the GPIO directly (0).
72 /* Is the pin input controlled by a peripheral(1) or the GPIO(0) */
74 /* If input_override, is the peripheral configuring the input buffer as connected (1) or disconnect…
77 /* Is "dir" controlled by a peripheral(1) or the GPIO(0) */
79 /* If dir_override is set, is the peripheral configuring the output as connected (1) or disconnecte…
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DNHW_EGU.c103 int int_mask = (EGU_regs->INTEN >> i) & 1; in nhw_egu_eval_interrupt()
127 EGU_regs->EVENTS_TRIGGERED[event_nbr] = 1; in nhw_egu_signal_EVENTS_TRIGGERED()
244 void nhw_egu_0_TASK_TRIGGER_1(void){ nhw_egu_TASK_TRIGGER(0,1); } in nhw_egu_0_TASK_TRIGGER_1()
259 void nhw_egu_1_TASK_TRIGGER_0(void){ nhw_egu_TASK_TRIGGER(1,0); } in nhw_egu_1_TASK_TRIGGER_0()
260 void nhw_egu_1_TASK_TRIGGER_1(void){ nhw_egu_TASK_TRIGGER(1,1); } in nhw_egu_1_TASK_TRIGGER_1()
261 void nhw_egu_1_TASK_TRIGGER_2(void){ nhw_egu_TASK_TRIGGER(1,2); } in nhw_egu_1_TASK_TRIGGER_2()
262 void nhw_egu_1_TASK_TRIGGER_3(void){ nhw_egu_TASK_TRIGGER(1,3); } in nhw_egu_1_TASK_TRIGGER_3()
263 void nhw_egu_1_TASK_TRIGGER_4(void){ nhw_egu_TASK_TRIGGER(1,4); } in nhw_egu_1_TASK_TRIGGER_4()
264 void nhw_egu_1_TASK_TRIGGER_5(void){ nhw_egu_TASK_TRIGGER(1,5); } in nhw_egu_1_TASK_TRIGGER_5()
265 void nhw_egu_1_TASK_TRIGGER_6(void){ nhw_egu_TASK_TRIGGER(1,6); } in nhw_egu_1_TASK_TRIGGER_6()
[all …]
DNHW_UART.c28 * (it does not take ~1 us as in the real HW)
225 bs_time_t duration = 1 + 8 + 1; /* Start bit, byte, and at least 1 stop bit */ in nhw_uarte_one_byte_time()
229 duration +=1; in nhw_uarte_one_byte_time()
232 duration +=1; in nhw_uarte_one_byte_time()
242 duration = (double)duration * 1e6 / 921600 + 0.5; in nhw_uarte_one_byte_time()
245 duration = (double)duration * 1e6 / 460800 + 0.5; in nhw_uarte_one_byte_time()
251 duration = (double)duration * 1e6 / 230400 + 0.5; in nhw_uarte_one_byte_time()
254 duration = (double)duration * 1e6 / 115200 + 0.5; in nhw_uarte_one_byte_time()
257 duration = (double)duration * 1e6 / 76800 + 0.5; in nhw_uarte_one_byte_time()
260 duration = (double)duration * 1e6 / 57600 + 0.5; in nhw_uarte_one_byte_time()
[all …]
Dirq_ctrl.c123 * If none, return -1
130 return -1; in hw_irq_ctrl_get_highest_prio_irq()
134 int winner = -1; in hw_irq_ctrl_get_highest_prio_irq()
138 int irq_nbr = nsi_find_lsb_set64(irq_status) - 1; in hw_irq_ctrl_get_highest_prio_irq()
140 irq_status &= ~((uint64_t) 1 << irq_nbr); in hw_irq_ctrl_get_highest_prio_irq()
206 nhw_intctrl_st[inst].irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
211 * return 1 is enabled, 0 is disabled.
218 return (nhw_intctrl_st[inst].irq_mask & ((uint64_t)1 << irq))?1:0; in hw_irq_ctrl_is_irq_enabled()
243 this->irq_status &= ~((uint64_t)1<<irq); in hw_irq_ctrl_clear_irq()
244 this->irq_premask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_clear_irq()
[all …]
DNHW_AES_CCM.c15 * 1. This model does not try to account for the delay the real CCM HW block has
105 uint8_t packet_direction, // Direction of packet (1:master to slave, 0: slave to master) in nonce_calc()
112 for (i = 0; i < NONCE_LEN - IV_LEN - 1; i++) in nonce_calc()
117 ccm_nonce[i] = (packet_counter & 0x7F) | (packet_direction == 1 /*master to slave*/ ? 0x80 : 0); in nonce_calc()
142 length = inptr[1]; in nrf_ccm_encrypt_tx()
147 outptr[1] = length; in nrf_ccm_encrypt_tx()
148 pkt_direction = cnfptr[24] & 1; in nrf_ccm_encrypt_tx()
157 &outptr[3], //encrypted payload (and MIC if generate_mic==1) in nrf_ccm_encrypt_tx()
158 …length, //including MIC length if ( generate_mic == 1 ) ; [ just the length in the output pa… in nrf_ccm_encrypt_tx()
194 length = inptr[1]; in nrf_ccm_decrypt_rx()
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DNHW_RADIO_utils.c42 check = (1 << RADIO_PCNF1_WHITEEN_Pos) in nrfra_check_pcnf1_ble()
49 "%s w 1|2Mbps BLE modulation only the BLE packet format is supported so far (PCNF1=%u)\n", in nrfra_check_pcnf1_ble()
62 | ( 1 << RADIO_PCNF0_S0LEN_Pos ) in nrfra_check_ble1M_conf()
68 "NRF_RADIO: For 1 Mbps only BLE packet format is supported so far (PCNF0=%u)\n", in nrfra_check_ble1M_conf()
85 | ( 1 << RADIO_PCNF0_S0LEN_Pos ) in nrfra_check_ble2M_conf()
137 | (0 << RADIO_PCNF1_BALEN_Pos) // => 1 byte for SFD in nrfra_check_802154_conf()
169 "NRF_RADIO: Only 1&2 Mbps BLE & 802.15.4 packet formats supported so far (MODE=%u)\n", in nhwra_check_packet_conf()
200 return 1; in nhwra_is_HW_TIFS_enabled()
237 preamble_length = 1; //1 byte in nhwra_prep_rx_request()
241 bits_per_us = 1; in nhwra_prep_rx_request()
[all …]
DNHW_UART_backend_fifo.c62 * (Note the smallest byte time is 10 micros at 1Mbps no parity and 1 stop bit,
68 #define TX_MIN_DELTA_RATIO 1
94 bool last_rx_msg_pending; /* The message in last_rx_msg is between pre and post processing (1)
125 u_el->fifo_tx = -1; in nhw_ufifo_backend_init()
126 u_el->fifo_rx = -1; in nhw_ufifo_backend_init()
163 if ((res == -1) && (errno == EPIPE)) { in write_to_tx_fifo()
485 * (1) We pick all old messages, and the first that points at now or the future in nhw_ufifo_handle_RxTimer()
503 * => when we come back to nhw_ufifo_handle_RxTimer() thru (1) in nhw_ufifo_handle_RxTimer()
541 if (uf_mdt < 1 || uf_mdt > 1e6) { in uf_parse_mdt()
542 bs_trace_error_line("uart_fifob_mdt must be set to a value between 1 and 1e6 (%s)\n", argv); in uf_parse_mdt()
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DNHW_AAR.c42 #if NHW_AAR_TOTAL_INST > 1
43 #error "This model only supports 1 instance so far"
98 Timer_AAR = nsi_hws_get_time() + 1 + NHW_AAR_t_AAR * n_irks; /*AAR delay*/ in NHW_SIGNAL_EVENT_si()
133 if (matching_irk != -1) { in NHW_SIDEEFFECTS_EVENTS()
145 uint32_t value = ptr[0] | (ptr[1] << 8) | (ptr[2] << 16); in read_3_bytes_value()
155 * or to -1 if none did.
170 *good_irk = -1; in nhw_aar_resolve()
174 address_ptr[2], address_ptr[1], address_ptr[0]); in nhw_aar_resolve()
210 return i+1; in nhw_aar_resolve()
Dtrivial_xo.c33 time_off = ((double)t_off)/1e6; in xo_model_set_toffset()
63 bs_trace_warning_line("Very high clock drift set (%0.f ppm > 300ppm)\n", xo_drift*1e6); in trivial_xo_init()
64 if ((xo_drift < -1e-2) || (xo_drift > 1e-2)) { in trivial_xo_init()
65 bs_trace_error_line("Insane clock drift set (%0.f ppm)\n", xo_drift*1e6); in trivial_xo_init()
DNHW_RADIO.c13 …* Note: as of now, only 1&2Mbps BLE & 15.4 packet formats are supported, there is quite many notes…
34 * if CRCINC==1, the CRC LEN is deducted from the length field, before MAXLEN is checked.
64 * and somewhere during the address for 1&2Mbps BLE.
117 * (1) Here the response may be that:
128 * and continue from (1).
168 #if NHW_RADIO_TOTAL_INST > 1
169 #error "This model only supports 1 instance so far"
234 NRF_RADIO_regs.POWER = 1; in radio_reset()
243 bits_per_us = 1; in nhw_radio_init()
274 nhwra_set_Timer_RADIO(nsi_hws_get_time() + nhwra_timings_get_rampup_time(1, from_hw_tifs)); in nhw_RADIO_TASK_TXEN()
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DNHW_53_FICR.c39 NRF_FICR_APP_regs.INFO.DEVICEID[1] = bs_random_uint32(); in nhw_53_ficr_init()
41 NRF_FICR_APP_regs.INFO.FLASH = 0x400; /*1 MB*/ in nhw_53_ficr_init()
47 NRF_FICR_NET_regs.INFO.DEVICEID[1] = NRF_FICR_APP_regs.INFO.DEVICEID[1]; in nhw_53_ficr_init()
59 NRF_FICR_NET_regs.DEVICEADDR[1] = bs_random_uint32(); in nhw_53_ficr_init()
DNHW_RTC.c28 * immediately (in HW it takes between 1/2 and 1+1/2 LFCLKs:
32 * they can be raised relatively at +-1/2 LFCLK or +-1/2 PCLK16M of each other)
112 #define LF_CLOCK_PERIOD_us 31 /* the LF clock period in us ceil(1e6/32768) = ceil(30.517578125u…
220 if(sub_us_time % (1U << SUB_US_BITS) != 0) //rounding up in sub_us_time_to_us_time()
222 us_time += 1; in sub_us_time_to_us_time()
265 ticks = delta_sub_us / ((uint64_t)LF_CLOCK_PERIOD_subus * (nhw_rtc_st[rtc].PRESC + 1)); in time_sub_us_to_counter()
275 Elapsed = counter * (uint64_t)LF_CLOCK_PERIOD_subus * (nhw_rtc_st[rtc].PRESC + 1); in counter_to_time_sub_us()
281 * Return the time in sub-microsecond units it takes for the COUNTER to do 1 wrap
284 return counter_to_time_sub_us(rtc, (uint64_t)RTC_COUNTER_MASK + 1); in time_of_1_counter_wrap_sub_us()
369 …this->overflow_timer = get_counter_match_time(rtc, RTC_COUNTER_MASK + 1, &this->overflow_timer_sub… in update_overflow_timer()
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DNHW_TIMER.c170 case 1: in mask_from_bitmode()
183 * Return the time in us it takes for the COUNTER to do 1 wrap
187 return counter_to_time((uint64_t)mask_from_bitmode(t) + 1, t); in time_of_1_counter_wrap()
361 TIMER_regs->EVENTS_COMPARE[cc] = 1; in nhw_timer_signal_COMPARE()
371 case 1: in nhw_timer_signal_COMPARE()
407 this->Counter = (this->Counter + 1) & mask_from_bitmode(t); in nhw_timer_TASK_COUNT()
583 void nhw_timer1_TASK_START(void) { nhw_timer_TASK_START(1); } in nhw_timer1_TASK_START()
589 void nhw_timer1_TASK_STOP(void) { nhw_timer_TASK_STOP(1); } in nhw_timer1_TASK_STOP()
595 void nhw_timer0_TASK_CAPTURE_1(void) { nhw_timer_TASK_CAPTURE(0,1); } in nhw_timer0_TASK_CAPTURE_1()
599 void nhw_timer1_TASK_CAPTURE_0(void) { nhw_timer_TASK_CAPTURE(1,0); } in nhw_timer1_TASK_CAPTURE_0()
[all …]
DNRF_HWLowL.c32 phy_t = (bs_time_t)(1e6*phy_time_from_dev(((long double)d_t)*1e-6 ) + 0.5); in hwll_phy_time_from_dev()
47 dev_t = (bs_time_t)(1e6*dev_time_from_phy(((long double)p_t)*1e-6 ) + 0.5); in hwll_dev_time_from_phy()
70 //rounding of the clock drift + 1 us extra in case the next Tx or Rx in hwll_sync_time_with_phy()
DBLECrypt_if.h31 uint8_t* encrypted_payload, //encrypted payload (and MIC if generate_mic==1)
32 …int length, //including MIC length if ( generate_mic == 1 ) ; [ just the length in the pac…
41 …int length, //including MIC lenght if (has_mic == 1) ; [ just the length in the packet head…
45 uint8_t *mic_error /*was there a mic error in the packet (only if has_mic==1)*/
DNHW_MUTEX.c48 MUTEX_state[n] = 1; in nhw_MUTEX_regr_sideeffects_MUTEX()
49 NRF_MUTEX_regs.MUTEX[n] = 1; in nhw_MUTEX_regr_sideeffects_MUTEX()
52 return 1; in nhw_MUTEX_regr_sideeffects_MUTEX()
DNHW_NVM_backend.c35 st->fd = -1; in nhw_nvm_initialize_data_storage()
45 if (st->fd == -1) { in nhw_nvm_initialize_data_storage()
56 if (ftruncate(st->fd, st->size) == -1) { in nhw_nvm_initialize_data_storage()
107 if (st->fd != -1) { in nhw_nvm_clear_storage()
109 st->fd = -1; in nhw_nvm_clear_storage()
/nrf_hw_models-3.6.0/docs/
DGPIO.md39 * Port is the GPIO port number starting from 0 (for a nrf52833: 0 or 1).
40 * Pin is the pin number in that port (for a nrf52833: 0..31 for port 0, and 0..9 for port 1)
41 * Level is either 0 (for low) or 1 (for high)
47 0,0,0,1
49 600,0,0,1
51 1000,0,0,1
53 101624,0,0,1
56 Where pin 0 in port 0, is toggled at boot, 200microseconds, 600microseconds, 800microseconds, 1ms
85 To short pin 1 from port 0, to both pins 2 and 3 from port 1,<br>
90 to short pin 0 from port 1 to pin 2 from port 2.
/nrf_hw_models-3.6.0/src/nrfx/drivers/
Dnrfx_common.c41 } else if (IS_PERIPHERAL_REG(p_reg, TIMER, 1,)) { in nrfx_get_irq_number()
58 } else if (IS_PERIPHERAL_REG(p_reg, RTC, 1,)) { in nrfx_get_irq_number()
63 } else if (IS_PERIPHERAL_REG(p_reg, EGU, 1,)) { in nrfx_get_irq_number()
83 } else if (IS_PERIPHERAL_REG(p_reg, UARTE, 1,)) { in nrfx_get_irq_number()
123 } else if (IS_PERIPHERAL_REG(p_reg, RTC, 1, _NS)) { in nrfx_get_irq_number()
125 } else if (IS_PERIPHERAL_REG(p_reg, TIMER, 1, _NS)) { in nrfx_get_irq_number()
131 } else if (IS_PERIPHERAL_REG(p_reg, SWI, 1, _NS)) { in nrfx_get_irq_number()
144 /* 1 CACHE */ in nrfx_get_irq_number()
152 } else if (IS_PERIPHERAL_REG(p_reg, UARTE, 1, _S)) { in nrfx_get_irq_number()
164 } else if (IS_PERIPHERAL_REG(p_reg, TIMER, 1, _S)) { in nrfx_get_irq_number()
[all …]
/nrf_hw_models-3.6.0/src/nrfx/hal/
Dnrf_ppi.c14 p_reg->CHENSET = (1 << channel); in nrf_ppi_channel_enable()
20 p_reg->CHENCLR = (1 << channel); in nrf_ppi_channel_disable()
73 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1; in nrf_ppi_group_disable()
79 p_reg->TASKS_CHG[(uint32_t) group].EN = 1; in nrf_ppi_group_enable()
Dnrf_nvmc.c38 p_reg->ERASEUICR = 1; in nrf_nvmc_uicr_erase_start()
47 p_reg->ERASEALL = 1; in nrf_nvmc_erase_all_start()
101 bs_time_t wait = nhw_nvmc_time_to_ready(inst) + 1; in nrf_nvmc_ready_wait()
102 wait = BS_MAX(BS_MIN(wait,100),1); in nrf_nvmc_ready_wait()

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