12  *  * Note a.1:
24  *  * Note b.1:
60 static uint32_t INPUT_mask[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].INPUT (0: enabled; 1: disable…
61 static uint32_t SENSE_mask[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].SENSE.en (1: enabled; 0: disa…
62 static uint32_t SENSE_inv[NRF_GPIOS];  /* As a 32bit mask, PIN_CNF[*].SENSE.inv (1: inverted;0: not…
65  * Is the output driven by another peripheral (1) or the GPIO directly (0).
72 /* Is the pin input controlled by a peripheral(1) or the GPIO(0) */
74 /* If input_override, is the peripheral configuring the input buffer as connected (1) or disconnect…
77 /* Is "dir" controlled by a peripheral(1) or the GPIO(0) */
79 /* If dir_override is set, is the peripheral configuring the output as connected (1) or disconnecte…
169  *		* -1 : Don't change
171  *		*  1 : Take external control of pin output value (peripheral sets the output value
174  *		* -1 : Don't change
179  *		* -1 : Don't change
186  *              * -1: Don't change
188  *              *  1: high
198 	uint32_t mask = 1<<n;  in nrf_gpio_peri_pin_control()
204 		out_override[port] |= (uint32_t)(override_output?1:0) << n;  in nrf_gpio_peri_pin_control()
209 		input_override[port] |= (uint32_t)(override_input?1:0) << n;  in nrf_gpio_peri_pin_control()
212 		input_override_connected[port] |= (uint32_t)(override_input==3?1:0) << n;  in nrf_gpio_peri_pin_control()
218 		dir_override[port] |= (uint32_t)(override_dir?1:0) << n;  in nrf_gpio_peri_pin_control()
221 		dir_override_set[port] |= (uint32_t)(override_dir==3?1:0) << n;  in nrf_gpio_peri_pin_control()
227 		external_OUT[port] &= ~((uint32_t)1 << n);  in nrf_gpio_peri_pin_control()
228 		external_OUT[port] |= (uint32_t)(new_level?1:0) << n;  in nrf_gpio_peri_pin_control()
253 	if (((out_override[port] >> n) & 0x1) != 1) { /* LCOV_EXCL_START */  in nrf_gpio_peri_change_output()
259 	if (((get_dir(port) >> n) & 0x1) != 1) {  in nrf_gpio_peri_change_output()
266 	external_OUT[port] &= ~((uint32_t)1 << n);  in nrf_gpio_peri_change_output()
339 	for (int n = __builtin_ffs(diff) - 1; n >= 0; n = __builtin_ffs(diff) - 1) {  in nrf_gpio_eval_inputs()
341 		diff &= ~(1 << n);  in nrf_gpio_eval_inputs()
380 	IO_level[port] ^= (uint32_t)1 << n;  in nrf_gpio_eval_input()
420 	for (int n = __builtin_ffs(diff) - 1; n >= 0; n = __builtin_ffs(diff) - 1) {  in nrf_gpio_eval_outputs()
422 		diff &= ~(1 << n);  in nrf_gpio_eval_outputs()
485 	/* Whatever bits SW set to 1, it is trying to clear: */  in nrf_gpio_regw_sideeffects_LATCH()
497 	 *   If one or more bits in the LATCH register are '1' after the CPU has  in nrf_gpio_regw_sideeffects_LATCH()
500 	 * "the CPU has performed a clear operation" == after writing LATCH with any bit to 1  in nrf_gpio_regw_sideeffects_LATCH()
502 	if (sw_input != 0 && LDETECT[port] != 0 && NRF_GPIO_regs[port].DETECTMODE == 1) {  in nrf_gpio_regw_sideeffects_LATCH()
520 		NRF_GPIO_regs[port].DIR ^= 1 << n;  in nrf_gpio_regw_sideeffects_PIN_CNF()
535 		INPUT_mask[port] ^= 1 << n;  in nrf_gpio_regw_sideeffects_PIN_CNF()
541 	if (((sense >> 1) & 0x1) != ((SENSE_mask[port] >> n) & 0x1)) {  in nrf_gpio_regw_sideeffects_PIN_CNF()
542 		SENSE_mask[port] ^= 1 << n;  in nrf_gpio_regw_sideeffects_PIN_CNF()
546 		SENSE_inv[port] ^= 1 << n;  in nrf_gpio_regw_sideeffects_PIN_CNF()