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/Zephyr-Core-3.4.0/dts/arm/nxp/
Dnxp_lpc55S6x_ns.dtsi10 ranges = <0x4000000 0x4000000 0x20000000>;
14 ranges = <0x0 0x40000000 0x10000000>;
Dnxp_lpc55S16_ns.dtsi10 ranges = <0x4000000 0x4000000 0x20000000>;
14 ranges = <0x0 0x40000000 0x10000000>;
Dnxp_lpc55S36_ns.dtsi10 ranges = <0x4000000 0x4000000 0x20000000>;
14 ranges = <0x0 0x40000000 0x10000000>;
27 reg = <0x20000000 DT_SIZE_K(112)>;
Dnxp_lpc55S06_ns.dtsi10 ranges = <0x4000000 0x4000000 0x20000000>;
14 ranges = <0x0 0x40000000 0x10000000>;
23 reg = <0x40000000 DT_SIZE_K(16)>;
37 reg = <0x20000000 DT_SIZE_K(80)>;
Dnxp_lpc55S2x.dtsi15 ranges = <0x4000000 0x4000000 0x20000000>;
19 ranges = <0x0 0x40000000 0x10000000>;
22 ranges = <0x0 0x10000000 0x3020000>;
Dnxp_lpc55S6x.dtsi15 ranges = <0x4000000 0x14000000 0x20000000>;
19 ranges = <0x0 0x50000000 0x10000000>;
22 ranges = <0x0 0x10000000 0x3020000>;
Dnxp_lpc55S1x_common.dtsi16 #size-cells = <0>;
18 cpu@0 {
20 reg = <0>;
26 reg = <0xe000ed90 0x40>;
39 reg = <0x4000000 DT_SIZE_K(16)>;
44 reg = <0x20000000 DT_SIZE_K(32)>;
49 reg = <0x20008000 DT_SIZE_K(16)>;
55 reg = <0x2000c000 DT_SIZE_K(16)>;
62 reg = <0x20010000 DT_SIZE_K(16)>;
72 syscon: syscon@0 {
[all …]
Dnxp_lpc55S2x_common.dtsi25 #size-cells = <0>;
27 cpu@0 {
29 reg = <0>;
35 reg = <0xe000ed90 0x40>;
48 reg = <0x4000000 DT_SIZE_K(32)>;
53 reg = <0x20000000 DT_SIZE_K(64)>;
58 reg = <0x20010000 DT_SIZE_K(64)>;
64 reg = <0x20020000 DT_SIZE_K(64)>;
70 reg = <0x20040000 DT_SIZE_K(16)>;
76 reg = <0x40100000 DT_SIZE_K(16)>;
[all …]
Dnxp_lpc55S6x_common.dtsi26 #size-cells = <0>;
28 cpu@0 {
30 reg = <0>;
36 reg = <0xe000ed90 0x40>;
53 reg = <0x4000000 DT_SIZE_K(32)>;
66 reg = <0x20000000 DT_SIZE_K(64)>;
71 reg = <0x20010000 DT_SIZE_K(64)>;
76 reg = <0x20020000 DT_SIZE_K(64)>;
81 reg = <0x20030000 DT_SIZE_K(64)>;
86 reg = <0x20040000 DT_SIZE_K(16)>;
[all …]
/Zephyr-Core-3.4.0/samples/subsys/ipc/openamp/boards/
Dlpcxpresso54114_m4.overlay18 reg = <0x4000000 0x8000>;
/Zephyr-Core-3.4.0/samples/subsys/ipc/openamp/remote/boards/
Dlpcxpresso54114_m0.overlay18 reg = <0x4000000 0x8000>;
/Zephyr-Core-3.4.0/dts/xtensa/
Dsample_controller.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
17 reg = <0>;
24 reg = <0x60000000 0x4000000>;
/Zephyr-Core-3.4.0/tests/application_development/code_relocation/
Dlinker_xtensa_qemu_sram2.ld14 #define RAM_SIZE2 (0x4000000)
/Zephyr-Core-3.4.0/boards/arm/actinius_icarus/
Dactinius_icarus_common_2_0_0.dtsi10 psels = <NRF_PSEL(UART_TX, 0, 9)>,
11 <NRF_PSEL(UART_RX, 0, 6)>;
17 psels = <NRF_PSEL(UART_TX, 0, 9)>,
18 <NRF_PSEL(UART_RX, 0, 6)>;
29 w25q64: w25q64jv@0 {
31 reg = <0>;
34 size = <0x4000000>;
/Zephyr-Core-3.4.0/arch/x86/zefi/
Defi.ld13 . = 0x4000000;
/Zephyr-Core-3.4.0/dts/nios2/intel/
Dnios2f.dtsi9 #size-cells = <0>;
11 cpu: cpu@0 {
14 reg = <0>;
20 flash0: flash@0 {
22 reg = <0x00 0xb8000>;
27 reg = <0x400000 0x20000>;
39 reg = <0x100000 0x400>;
41 interrupts = <1 0>;
48 reg = <0x201000 0x8>;
57 #size-cells = <0>;
[all …]
/Zephyr-Core-3.4.0/dts/bindings/flash_controller/
Dst,stm32-qspi-nor.yaml9 mx25r6435f: qspi-nor-flash@0 {
11 reg = <0>;
13 size = <0x4000000>;
56 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
57 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
/Zephyr-Core-3.4.0/tests/bluetooth/controller/common/include/
Dhelper_features.h13 #define FEAT_ENCODED 0x01
15 #define FEAT_ENCODED 0x00
19 #define FEAT_PARAM_REQ 0x02
21 #define FEAT_PARAM_REQ 0x00
25 #define FEAT_EXT_REJ 0x04
27 #define FEAT_EXT_REJ 0x00
31 #define FEAT_PERIPHERAL_FREQ 0x08
33 #define FEAT_PERIPHERAL_FREQ 0x00
37 #define FEAT_PING 0x10
39 #define FEAT_PING 0x00
[all …]
/Zephyr-Core-3.4.0/dts/arm64/qemu/
Dqemu-virt-a53.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
58 #clock-cells = <0>;
70 reg = <0x00 0x8000000 0x00 0x010000>,
71 <0x00 0x80a0000 0x00 0xf60000>;
75 #size-cells = <0x02>;
76 #address-cells = <0x02>;
80 reg = <0x00 0x8080000 0x00 0x20000>;
87 reg = <0x00 0x9000000 0x00 0x1000>;
[all …]
Dqemu-virt-arm64.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
58 #clock-cells = <0>;
70 reg = <0x00 0x8000000 0x00 0x010000>,
71 <0x00 0x80a0000 0x00 0xf60000>;
75 #size-cells = <0x02>;
76 #address-cells = <0x02>;
80 reg = <0x00 0x8080000 0x00 0x20000>;
87 reg = <0x00 0x9000000 0x00 0x1000>;
[all …]
/Zephyr-Core-3.4.0/boards/arm/actinius_icarus_som_dk/
Dactinius_icarus_som_dk_common.dtsi32 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
83 pinctrl-0 = <&uart0_default>;
92 pinctrl-0 = <&neopixel_spi_default>;
96 neopixel_led: ws2812@0 {
99 reg = <0>; /* ignored, but necessary for SPI bindings */
106 spi-one-frame = <0x70>;
107 spi-zero-frame = <0x40>;
117 pinctrl-0 = <&i2c2_default>;
122 reg = <0x19>;
134 pinctrl-0 = <&spi3_default>;
[all …]
/Zephyr-Core-3.4.0/boards/arm/actinius_icarus_bee/
Dactinius_icarus_bee_common.dtsi41 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
107 pinctrl-0 = <&uart0_default>;
118 pinctrl-0 = <&i2c2_default>;
123 reg = <0x19>;
135 pinctrl-0 = <&spi3_default>;
138 w25q64: w25q64jv@0 {
140 reg = <0>;
143 size = <0x4000000>;
153 pinctrl-0 = <&pwm0_default>;
164 boot_partition: partition@0 {
[all …]
/Zephyr-Core-3.4.0/samples/arch/mpu/mpu_test/src/
Dmain.c21 #define RESERVED_MEM_MAP (CONFIG_SRAM_BASE_ADDRESS + 0x4000000)
47 return 0; in cmd_read()
60 offset = FLASH_MEM + 0x20000; in cmd_write_mcux()
61 value[0] = 0xBADC0DE; in cmd_write_mcux()
62 value[1] = 0xBADC0DE; in cmd_write_mcux()
64 PR_SHELL(sh, "write address: 0x%x\n", offset); in cmd_write_mcux()
67 sizeof(value)) != 0) { in cmd_write_mcux()
72 return 0; in cmd_write_mcux()
82 uint32_t offset = FLASH_MEM + 0x4000; in cmd_write_stm32()
83 uint32_t value = 0xBADC0DE; in cmd_write_stm32()
[all …]
/Zephyr-Core-3.4.0/boards/arm/disco_l475_iot1/
Ddisco_l475_iot1.dts116 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
122 pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pa1>;
129 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
136 pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
143 reg = <0x1e>;
148 reg = <0x5f>;
154 reg = <0x5d>;
159 reg = <0x6a>;
165 reg = <0x29>;
171 pinctrl-0 = <&i2c3_scl_pc0 &i2c3_sda_pc1>;
[all …]
/Zephyr-Core-3.4.0/soc/arm/nxp_lpc/lpc55xxx/
Dsoc.c50 .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(3072U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
100 CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); in clock_init()
120 CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 0U, true); in clock_init()
128 CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 0U, true); in clock_init()
178 *((uint32_t *)(USBFSH_BASE + 0x5C)) |= USBFSH_PORTMODE_DEV_ENABLE_MASK; in clock_init()
185 memset((uint8_t *)FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USB_USB_RAM); in clock_init()
194 *((uint32_t *)(USBHSH_BASE + 0x50)) = USBHSH_PORTMODE_SW_PDCOM_MASK; in clock_init()
199 *((uint32_t *)(USBHSH_BASE + 0x50)) |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in clock_init()
205 CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); in clock_init()
208 memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM); in clock_init()
[all …]

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