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/Zephyr-Core-3.6.0/boards/riscv/riscv32_virtual/support/
Driscv32_virtual.repl4 flash: Memory.MappedMemory @ sysbus 0x80000000
5 size: 0x400000
7 ddr: Memory.MappedMemory @ sysbus 0x80400000
8 size: 0x400000
10 uart0: UART.NS16550 @ sysbus 0x10000000
13 uart1: UART.NS16550 @ sysbus 0x10000100
21 plic0: IRQControllers.PlatformLevelInterruptController @ sysbus 0x0C000000
22 0 -> cpu@11
26 plic1: IRQControllers.PlatformLevelInterruptController @ sysbus 0x08000000
27 0 -> cpu@4
[all …]
/Zephyr-Core-3.6.0/boards/x86/qemu_x86/
DKconfig.defconfig25 default 0x10000000 if ACPI
50 default 0x10000000 if ACPI
60 default 0x400000
84 default 0x400000
112 default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0)
Dqemu_x86_virt_defconfig18 CONFIG_SRAM_OFFSET=0x100000
19 CONFIG_KERNEL_VM_SIZE=0x400000
20 CONFIG_KERNEL_VM_BASE=0x40000000
21 CONFIG_KERNEL_VM_OFFSET=0
Dqemu_x86_tiny_defconfig22 CONFIG_KERNEL_VM_SIZE=0x400000
23 CONFIG_KERNEL_VM_BASE=0x40000000
24 CONFIG_KERNEL_VM_OFFSET=0x100000
25 CONFIG_SRAM_OFFSET=0
/Zephyr-Core-3.6.0/soc/arm64/intel_socfpga/agilex5/
DKconfig.defconfig.agilex520 default 0x400000
/Zephyr-Core-3.6.0/dts/nios2/intel/
Dnios2-qemu.dtsi8 #size-cells = <0>;
10 cpu: cpu@0 {
13 reg = <0>;
21 reg = <0x420000 0x20000>;
26 reg = <0x400000 0x20000>;
38 reg = <0x201000 0x400>;
39 interrupts = <0>;
45 reg = <0x440000 0x400>;
Dnios2f.dtsi9 #size-cells = <0>;
11 cpu: cpu@0 {
14 reg = <0>;
20 flash0: flash@0 {
22 reg = <0x00 0xb8000>;
27 reg = <0x400000 0x20000>;
39 reg = <0x100000 0x400>;
41 interrupts = <1 0>;
48 reg = <0x201000 0x8>;
57 #size-cells = <0>;
[all …]
/Zephyr-Core-3.6.0/subsys/lorawan/services/
DKconfig40 according to LoRa Alliance TS003-2.0.0.
53 range from 128 (0x80) to 4194304 (0x400000).
63 TS005-1.0.0 as published by the LoRa Alliance.
/Zephyr-Core-3.6.0/boards/arm/mps2_an385/
Dmps2_an385.dts33 gpios = <&gpio_led0 0>;
46 gpios = <&gpio_button 0>;
58 #size-cells = <0>;
60 cpu@0 {
62 reg = <0>;
68 reg = <0x20000000 0x400000>;
71 flash0: flash@0 {
73 reg = <0 0x400000>;
79 #clock-cells = <0>;
85 reg = <0x40000000 0x1000>;
[all …]
/Zephyr-Core-3.6.0/soc/nios2/nios2f-zephyr/include/
Dlinker.h68 #define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000
70 #define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
72 #define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
74 #define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
76 #define RESET_REGION_BASE 0x0
Dsystem.h64 #define ALT_CPU_BIG_ENDIAN 0
65 #define ALT_CPU_BREAK_ADDR 0x00200820
69 #define ALT_CPU_CPU_ID_VALUE 0x00000000
71 #define ALT_CPU_DATA_ADDR_WIDTH 0x1c
72 #define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
76 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
77 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
78 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
83 #define ALT_CPU_HARDWARE_MULX_PRESENT 0
94 #define ALT_CPU_INST_ADDR_WIDTH 0x1c
[all …]
/Zephyr-Core-3.6.0/soc/nios2/nios2-qemu/include/
Dlinker.h68 #define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
70 #define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
72 #define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
74 #define RESET_REGION_BASE 0x0
Dsystem.h53 #define ALT_CPU_BIG_ENDIAN 0
54 #define ALT_CPU_BREAK_ADDR 0x00200820
58 #define ALT_CPU_CPU_ID_VALUE 0x00000000
60 #define ALT_CPU_DATA_ADDR_WIDTH 0x17
61 #define ALT_CPU_DCACHE_LINE_SIZE 0
62 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
63 #define ALT_CPU_DCACHE_SIZE 0
64 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
65 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
66 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
[all …]
/Zephyr-Core-3.6.0/dts/bindings/mtd/
Datmel,sam-flash.yaml35 reg = <0x400e0a00 0x200>;
45 reg = <0x400000 0x100000>;
69 boot_partition: partition@0 {
71 reg = <0x0 0x10000>;
76 reg = <0x10000 0x70000>;
81 reg = <0x80000 0x70000>;
86 reg = <0xf0000 0x100000>;
/Zephyr-Core-3.6.0/tests/bluetooth/controller/common/include/
Dhelper_features.h13 #define FEAT_ENCODED 0x01
15 #define FEAT_ENCODED 0x00
19 #define FEAT_PARAM_REQ 0x02
21 #define FEAT_PARAM_REQ 0x00
25 #define FEAT_EXT_REJ 0x04
27 #define FEAT_EXT_REJ 0x00
31 #define FEAT_PERIPHERAL_FREQ 0x08
33 #define FEAT_PERIPHERAL_FREQ 0x00
37 #define FEAT_PING 0x10
39 #define FEAT_PING 0x00
[all …]
/Zephyr-Core-3.6.0/boards/arm/rm1xx_dvk/
Drm1xx_dvk.dts55 pinctrl-0 = <&i2c0_default>;
65 pinctrl-0 = <&spi0_default>;
76 pinctrl-0 = <&spi1_default>;
79 at25: at25df041b@0 {
81 reg = <0>;
84 size = <0x400000>;
85 has-lock = <0xbc>;
111 pinctrl-0 = <&uart0_default>;
123 boot_partition: partition@0 {
125 reg = <0x00000000 0x0000C000>;
[all …]
/Zephyr-Core-3.6.0/doc/hardware/arch/
Dx86.rst61 are both ``0x0``.
63 - ``CONFIG_SRAM_BASE_ADDRESS == 0x00000000`` and
64 ``CONFIG_KERNEL_VM_BASE = 0x40000000`` is valid, while
66 - ``CONFIG_SRAM_BASE_ADDRESS == 0x00000000`` and
67 ``CONFIG_KERNEL_VM_BASE = 0x20000000`` is not.
91 --map 0xA0000000,0x2000
92 --map 0x80000000,0x400000,LWUX,0xB0000000)
/Zephyr-Core-3.6.0/arch/xtensa/core/
Dmmu.c12 #define ASID_INVALID 0
27 __ASSERT_NO_MSG((((uint32_t)l1_page) & 0xfff) == 0); in compute_regs()
28 __ASSERT_NO_MSG((user_asid == 0) || ((user_asid > 2) && in compute_regs()
31 /* We don't use ring 1, ring 0 ASID must be 1 */ in compute_regs()
33 (user_asid << 16) | 0x000201; in compute_regs()
36 regs->ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000; in compute_regs()
91 "wsr %0, PTEVADDR\n" in xtensa_set_paging()
136 uint32_t idtlb_pte = (regs.ptevaddr & 0xe0000000) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
137 uint32_t idtlb_stk = (((uint32_t)&regs) & ~0xfff) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
138 uint32_t iitlb_pc = (((uint32_t)&z_xt_init_pc) & ~0xfff) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
[all …]
/Zephyr-Core-3.6.0/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
36 reg = <0>;
75 reg = <0x3fc7c000 0x50000>;
80 #address-cells = <0>;
83 reg = <0x600c2000 0x198>;
89 reg = <0x60023000 0x80>;
97 reg = <0x60008000 0x1000>;
113 reg = <0x60002000 0x1000>;
118 flash0: flash@0 {
[all …]
/Zephyr-Core-3.6.0/include/zephyr/arch/nios2/
Dnios2.h69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
[all …]
/Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/esp32/
Ddefault.ld35 #define FLASH_SIZE 0x400000
39 #define IROM_SEG_ORG 0x400D0020
40 #define IROM_SEG_LEN FLASH_SIZE-0x20
41 #define IROM_SEG_ALIGN 0x4
43 #define IROM_SEG_ORG 0x400D0000
45 #define IROM_SEG_ALIGN 0x10000
47 #define IRAM_SEG_LEN 0x20000
56 mcuboot_hdr (RX): org = 0x0, len = 0x20
57 metadata (RX): org = 0x20, len = 0x20
58 ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/l4/
Dstm32l4p5.dtsi15 reg = <0x20000000 DT_SIZE_K(320)>;
23 #clock-cells = <0>;
41 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
42 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
46 reg = <0x48000000 0x2400>;
52 reg = <0x48000c00 0x400>;
53 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
60 reg = <0x48001000 0x400>;
61 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
68 reg = <0x48001400 0x400>;
[all …]
/Zephyr-Core-3.6.0/soc/nios2/nios2f-zephyr/cpu/
Dghrd_10m50da.qsys24 value = "0";
45 value = "0";
201 value = "0";
270 value = "0";
287 <parameter name="generationId" value="0" />
295 <parameter name="systemHash" value="0" />
297 <parameter name="timeStamp" value="0" />
337 <parameter name="DMA_EXTRA" value="0" />
340 <parameter name="FIFO_HWFC" value="0" />
342 <parameter name="FIFO_SWFC" value="0" />
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f4/
Dstm32f4.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 #clock-cells = <0>;
97 reg = <0x40023c00 0x400>;
98 interrupts = <4 0>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f2/
Dstm32f2.dtsi28 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
79 reg = <0x40023c00 0x400>;
80 interrupts = <4 0>;
[all …]

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