Searched +full:0 +full:x40000 (Results 1 – 25 of 71) sorted by relevance
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26 reg = <0x00010000 0xa0000>;30 reg = <0x000b0000 0x40000>;34 reg = <0x00000000 0xa0000>;38 reg = <0x000a0000 0x40000>;49 reg = <0x20000000 DT_SIZE_K(448)>;53 reg = <0x20000000 0x40000>;57 reg = <0x20040000 0x30000>;
14 * 0x0000_0000 BL2 - MCUBoot (64 KB)15 * 0x0001_0000 Primary image area (448 KB):16 * 0x0001_0000 Secure image primary (256 KB)17 * 0x0005_0000 Non-secure image primary (192 KB)18 * 0x0008_0000 Secondary image area (448 KB):19 * 0x0008_0000 Secure image secondary (256 KB)20 * 0x000c_0000 Non-secure image secondary (192 KB)21 * 0x000f_0000 Protected Storage Area (16 KB)22 * 0x000f_4000 Internal Trusted Storage Area (8 KB)23 * 0x000f_6000 OTP / NV counters area (8 KB)[all …]
17 boot_partition: partition@0 {19 reg = <0x00000000 0x10000>;22 label = "image-0";23 reg = <0x00010000 0x40000>;27 reg = <0x00050000 0x40000>;31 reg = <0x00090000 0x30000>;35 reg = <0x000c0000 0x30000>;
19 boot_partition: partition@0 {21 reg = <0x00000000 0x10000>;24 label = "image-0";25 reg = <0x00010000 0x40000>;29 reg = <0x00050000 0x40000>;33 reg = <0x00090000 0x30000>;37 reg = <0x000c0000 0x30000>;
3 arcver=0x5410 nsim_isa_big_endian=023 nsim_isa_timer_0_int_level=025 nsim_isa_timer_1_int_level=036 nsim_isa_volatile_limit=037 nsim_isa_volatile_disable=048 nsim_isa_intvbase_preset=0x057 dccm_size=0x4000058 dccm_base=0x8000000060 iccm0_size=0x40000[all …]
17 -Xtimer0_level=019 -Xtimer1_level=027 -volatile_limit=038 -interrupt_base=0x047 -dccm_size=0x4000048 -dccm_base=0x8000000050 -iccm0_size=0x4000051 -iccm0_base=0x0000000079 -Xvec_fast=086 -Xvec_mem_topology=0[all …]
3 arcver=0x427 nsim_isa_big_endian=025 nsim_isa_fpu_fast_mpy_option=026 nsim_isa_fpu_fast_div_option=030 nsim_isa_timer_1_int_level=041 nsim_isa_intvbase_preset=0x046 dccm_size=0x2000047 dccm_base=0x8000000049 iccm0_size=0x4000050 iccm0_base=0x00000000[all …]
25 -Xtimer1_level=036 -interrupt_base=0x041 -dccm_size=0x2000042 -dccm_base=0x8000000044 -iccm0_size=0x4000045 -iccm0_base=0x0000000049 -dmac_registers=052 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
13 #size-cells = <0>;14 cpu@0 {15 clock-frequency = <0>;18 reg = <0>;22 #address-cells = <0>;37 reg = <0x80000000 0x40000>;42 reg = <0x80040000 0x40000>;48 reg = <0x44000000 0x10000>;52 compatible = "sifive,plic-1.0.0";53 #address-cells = <0>;[all …]
13 code_partition: partition@0 {14 reg = <0x0 DT_SIZE_K(256)>;20 reg = <0x40000 DT_SIZE_K(256)>;
13 code_partition: partition@0 {14 reg = <0x0 DT_SIZE_K(256)>;20 reg = <0x40000 DT_SIZE_K(128)>;
4 FlshmapAddr = 06 [IMAGE "0"]7 ImageLocation = 0x10012 SpiSignalControl = 0x0014 FwOffset = 015 FwLoadAddress = 0xE000016 FwEntryAddress = 024 ImageLocation = 0x4000029 SpiSignalControl = 0x0031 FwOffset = 0[all …]
26 reg = <0x0 0x40000>;30 reg = <0x90000 0x10>;34 reg = <0x90078 0x8>;
13 reg = <0x50000000 0x40000>;14 interrupts = <67 0>;16 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,20 ghwcfg1 = <0x00000000>;21 ghwcfg2 = <0x229ed520>;22 ghwcfg4 = <0x17f08030>;28 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
15 reg = <0x40006800 0x40000>;16 interrupts = <67 0>;23 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;30 #phy-cells = <0>;
15 reg = <0x50000000 0x40000>;16 interrupts = <67 0>;30 #phy-cells = <0>;
18 #define W5500_COMMON_REGS 0x000019 #define W5500_MR 0x0000 /* Mode Register */20 #define W5500_GW 0x000121 #define MR_RST 0x80 /* S/W reset */22 #define MR_PB 0x10 /* Ping block */23 #define MR_AI 0x02 /* Address Auto-Increment */24 #define MR_IND 0x01 /* Indirect mode */25 #define W5500_SHAR 0x0009 /* Source MAC address */26 #define W5500_IR 0x0015 /* Interrupt Register */27 #define W5500_COMMON_REGS_LEN 0x0040[all …]
13 reg = <0x50000000 0x40000>;14 interrupts = <67 0>;16 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,20 ghwcfg1 = <0x00000000>;21 ghwcfg2 = <0x229ed520>;22 ghwcfg4 = <0x17f08030>;29 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
43 reg = <0xc0000000 DT_SIZE_M(8)>;105 boot_partition: partition@0 {107 reg = <0x00000000 0x00010000>;111 * The flash starting at 0x00010000 and ending at112 * 0x0001ffff (sectors 16-31) is reserved for use117 reg = <0x00010000 0x00030000>;119 /* The arduino default bootloader occupies the address space 0x0 - 0x40000.121 * applications will be located at 0x40000 which will be loaded by the125 label = "image-0";126 reg = <0x00040000 0x00060000>;[all …]
18 * (XEN) Grant table range: 0x00000040200000-0x0000004024000025 reg = <0x0 0x40200000 0x0 0x40000>;26 interrupts = <GIC_PPI 0x0 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;33 * region for Domain-0 for every specific configuration. You can36 * (XEN) BANK[0] 0x00000058000000-0x00000060000000 (128MB)44 reg = <0x00 0x58000000 0x00 DT_SIZE_M(128)>;
14 * (XEN) Grant table range: 0x00000088080000-0x000000880c000021 reg = <0x0 0x88080000 0x0 0x40000>;22 interrupts = <GIC_PPI 0x0 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;29 * region for Domain-0 for every specific configuration. You can32 * (XEN) BANK[0] 0x00000060000000-0x00000070000000 (256MB)39 reg = <0x00 0x60000000 0x00 DT_SIZE_M(256)>;
