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/Zephyr-Core-3.5.0/tests/drivers/uart/uart_async_api/boards/
Dnucleo_f207zg.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
Dnucleo_f429zi.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
Dnucleo_f767zi.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
Dnucleo_f746zg.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
/Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/
Dnucleo_f746zg.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
11 slow@0 {
13 reg = <0>;
16 fast@0 {
18 reg = <0>;
Dnucleo_f767zi.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
11 slow@0 {
13 reg = <0>;
16 fast@0 {
18 reg = <0>;
Dnucleo_f207zg.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
15 slow@0 {
17 reg = <0>;
20 fast@0 {
22 reg = <0>;
Dnucleo_f411re.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
15 slow@0 {
17 reg = <0>;
20 fast@0 {
22 reg = <0>;
Dnucleo_f429zi.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
15 slow@0 {
17 reg = <0>;
20 fast@0 {
22 reg = <0>;
/Zephyr-Core-3.5.0/dts/bindings/dma/
Dst,stm32-dma-v1.yaml12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
20 0x0: MEM to MEM
21 0x1: MEM to PERIPH
22 0x2: PERIPH to MEM
23 0x3: reserved for PERIPH to PERIPH
25 0x0: no address increment between transfers
26 0x1: increment address between transfers
28 0x0: no address increment between transfers
29 0x1: increment address between transfers
[all …]