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Searched +full:0 +full:x20440 (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/dts/bindings/dma/
Dst,stm32-dmamux.yaml11 1. channel: the mux channel from 0 to <dma-channels> - 1
16 0x0: MEM to MEM
17 0x1: MEM to PERIPH
18 0x2: PERIPH to MEM
19 0x3: reserved for PERIPH to PERIPH
21 0x0: no address increment between transfers
22 0x1: increment address between transfers
24 0x0: no address increment between transfers
25 0x1: increment address between transfers
27 0x0: Byte (8 bits)
[all …]
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts31 gpios = <&gpioc 13 0>;
36 gpios = <&gpioc 14 0>;
41 gpios = <&gpioc 15 0>;
49 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
56 pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
63 pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
65 dmas = <&dma1 3 0x20440>, <&dma1 2 0x20480>;
69 led_strip_spi: b1414@0 {
73 reg = <0>; /* ignored, but necessary for SPI bindings */
87 pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7a3.dtsi37 reg = <0x40040000 0x40000>;
38 interrupts = <77 0>, <74 0>, <75 0>;
51 reg = <0x50001000 0x200>;
52 interrupts = <88 0>, <89 0>;
61 reg = <0x52005000 0x1000>;
62 interrupts = <92 0>;
67 #size-cells = <0>;
73 reg = <0x5200a000 0x1000>;
74 interrupts = <150 0>;
79 #size-cells = <0>;
[all …]