Lines Matching +full:0 +full:x20440
37 reg = <0x40040000 0x40000>;
38 interrupts = <77 0>, <74 0>, <75 0>;
51 reg = <0x50001000 0x200>;
52 interrupts = <88 0>, <89 0>;
61 reg = <0x52005000 0x1000>;
62 interrupts = <92 0>;
67 #size-cells = <0>;
73 reg = <0x5200a000 0x1000>;
74 interrupts = <150 0>;
79 #size-cells = <0>;
86 #size-cells = <0>;
87 reg = <0x58001400 0x400>;
89 <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>;
90 dmas = <&dmamux2 0 12 0x20440 &dmamux2 1 11 0x20480>;
92 interrupts = <86 0>;
97 nist-config = <0xf00d00>;
98 health-test-magic = <0x17590abc>;
99 health-test-config = <0x72ac>;
104 reg = <0x58006800 0x400>;
105 interrupts = <147 0>;
115 reg = <0x24000000 DT_SIZE_K(256)>;
121 reg = <0x24040000 DT_SIZE_K(384)>;
128 reg = <0x240A0000 DT_SIZE_K(384)>;
135 reg = <0x30000000 DT_SIZE_K(64)>;
142 reg = <0x30010000 DT_SIZE_K(64)>;
149 reg = <0x38000000 DT_SIZE_K(32)>;
155 reg = <0x20000000 DT_SIZE_K(128)>;
159 itcm: memory@0 {
161 reg = <0x00000000 DT_SIZE_K(64)>;
167 reg = <0x70000000 DT_SIZE_M(256)>; /* max addressable area */
174 #phy-cells = <0>;
178 ts-cal1-addr = <0x08FFF814>;
179 ts-cal2-addr = <0x08FFF818>;
185 vrefint-cal-addr = <0x08FFF810>;