Searched +full:0 +full:x1c8 (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-Core-3.4.0/dts/bindings/pinctrl/ |
| D | ti,k3-pinctrl.yaml | 17 e.g. for AM62x the pinctrl base address is 0xf4000.
18 The default UART0_RX pin is located at 0x000f41c8 (mux mode 0).
19 So the configuration would be "K3_PINMUX(0x1c8, PIN_INPUT, MUX_MODE_0)".
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| /Zephyr-Core-3.4.0/boards/arm64/phycore_am62x_a53/ |
| D | phycore_am62x_a53.dts | 22 cpu@0 {
38 reg = <0x82000000 DT_SIZE_M(1)>;
44 pinmux = <K3_PINMUX(0x1c8, PIN_INPUT, MUX_MODE_0)>;
47 pinmux = <K3_PINMUX(0x1cc, PIN_OUTPUT, MUX_MODE_0)>;
53 pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
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| /Zephyr-Core-3.4.0/drivers/clock_control/ |
| D | clock_control_renesas_cpg_mssr.h | 12 #define SRSTCLR(i) (0x940 + (i) * 4)
15 #define CPGWPR 0x900
19 0x110, 0x114, 0x118, 0x11c,
20 0x120, 0x124, 0x128, 0x12c,
21 0x980, 0x984, 0x988, 0x98c,
26 0x0A0, 0x0A8, 0x0B0, 0x0B8,
27 0x0BC, 0x0C4, 0x1C8, 0x1CC,
28 0x920, 0x924, 0x928, 0x92C,
32 #define CANFDCKCR 0x244
39 #define CANFDCKCR_DIVIDER_MASK 0x1FF
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| /Zephyr-Core-3.4.0/include/zephyr/arch/x86/ |
| D | intel_vtd.h | 15 #define VTD_VER_REG 0x000 /* Version */
16 #define VTD_CAP_REG 0x008 /* Capability */
17 #define VTD_ECAP_REG 0x010 /* Extended Capability */
18 #define VTD_GCMD_REG 0x018 /* Global Command */
19 #define VTD_GSTS_REG 0x01C /* Global Status */
20 #define VTD_RTADDR_REG 0x020 /* Root Table Address */
21 #define VTD_CCMD_REG 0x028 /* Context Command */
22 #define VTD_FSTS_REG 0x034 /* Fault Status */
23 #define VTD_FECTL_REG 0x038 /* Fault Event Control */
24 #define VTD_FEDATA_REG 0x03C /* Fault Event Data */
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| /Zephyr-Core-3.4.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_espi_saf.h | 13 #define MCHP_ESPI_SAF_BASE_ADDR 0x40008000u
14 #define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000u
24 #define MCHP_SAF_FL_CM_PRF_CS0_OFS 0x1b0u
25 #define MCHP_SAF_FL_CM_PRF_CS1_OFS 0x1b2u
27 #define MCHP_ESPI_SAF_BASE 0x40008000u
28 #define MCHP_ESPI_SAF_COMM_BASE 0x40071000u
29 #define MCHP_ESPI_SAF_COMM_MODE_OFS 0x2b8u
39 #define MCHP_SAF_ECP_CMD_OFS 0x18u
40 #define MCHP_SAF_ECP_CMD_MASK 0xff00ffffu
41 #define MCHP_SAF_ECP_CMD_PUT_POS 0
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