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/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/filtering/src/
Dfir_q7.pat2 0x00, 0x02, 0x04, 0x03, 0x02, 0xFE, 0xFD, 0xFC,
3 0xFD, 0x00, 0x02, 0x04, 0x03, 0x02, 0xFF, 0xFD,
4 0xFD, 0xFE, 0x00, 0x03, 0x04, 0x04, 0x01, 0xFF,
5 0xFC, 0xFC, 0xFD, 0x01, 0x03, 0x04, 0x03, 0x01,
6 0xFF, 0xFC, 0xFC, 0xFD, 0x00, 0x02, 0x04, 0x03,
7 0x02, 0xFF, 0xFD, 0xFC, 0xFE, 0x00
11 0x2B, 0x40, 0x20, 0x4D, 0x33, 0x1A, 0x55, 0x40,
12 0x2B, 0x15, 0x5B, 0x49, 0x37, 0x25, 0x12, 0x60,
13 0x50, 0x40, 0x30, 0x20, 0x10, 0x64, 0x55, 0x47,
14 0x39, 0x2B, 0x1C, 0x0E, 0x66, 0x5A, 0x4D, 0x40,
[all …]
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/matrix/src/
Dunary_q7.pat2 0xFB, 0x03, 0x09, 0x06, 0xF5, 0x03, 0x08, 0x0C,
3 0xFE, 0xFE, 0x0A, 0x02, 0xFF, 0x0B, 0x00, 0x0B,
4 0x08, 0x00, 0xFF, 0x0A, 0xFD, 0x06, 0x08, 0xF2,
5 0x0B, 0xEC, 0xF8, 0x05, 0xFE, 0x06, 0xE3, 0xF7,
6 0x0D, 0xF7, 0xF1, 0xEE, 0x15, 0xF0, 0xFE, 0x0B,
7 0xFE, 0x19, 0x04, 0x0C, 0x19, 0xFC, 0x05, 0xFB,
8 0xFC, 0x08, 0x10, 0x05, 0xFF, 0xFB, 0xF0, 0xEC,
9 0x01, 0x0C, 0x04, 0xF2, 0xFB, 0x0C, 0x00, 0xFB,
10 0x02, 0x07, 0xFE, 0xFE, 0x08, 0x09, 0xF8, 0x06,
11 0xED, 0xF4, 0xFE, 0x01, 0xFE, 0xFD, 0x07, 0xF9,
[all …]
Dbinary_q7.pat2 0x29, 0xFF, 0x63, 0x16, 0x2D, 0xFC, 0xDA, 0x05,
3 0xDE, 0x22, 0xDE, 0x06, 0x21, 0x11, 0x01, 0xC9,
4 0x29, 0xFC, 0x4B, 0x17, 0xD1, 0x48, 0xF8, 0x08,
5 0xA8, 0xFC, 0x17, 0xFF, 0x12, 0x15, 0x40, 0xC8,
6 0xD0, 0xA0, 0xE2, 0xEB, 0x0D, 0xF9, 0xD1, 0xD8,
7 0xF5, 0x2C, 0x08, 0xF3, 0xD9, 0x03, 0xD7, 0xE8,
8 0xFE, 0x2C, 0x0C, 0xF5, 0x2C, 0x14, 0xFC, 0xFB,
9 0xEE, 0x0C, 0xFC, 0x15, 0xD9, 0xE6, 0xFA, 0xF5,
10 0x10, 0x11, 0x0F, 0x13, 0xC9, 0xEF, 0x1C, 0xCB,
11 0xD5, 0xCA, 0x18, 0xF9, 0xFC, 0x03, 0xBA, 0x46,
[all …]
/Zephyr-Core-3.5.0/tests/net/lib/lwm2m/content_senml_cbor/src/
Dmain.c14 #define TEST_OBJ_ID 0xFFFF
15 #define TEST_OBJ_INST_ID 0
17 #define TEST_RES_S8 0
72 int i = 0, j = 0; in test_obj_create()
109 test_obj.version_minor = 0; in test_obj_init()
129 memset(&test_msg, 0, sizeof(test_msg)); in context_reset()
178 uint16_t offset = 0; in ZTEST()
179 int8_t value[] = { 0, INT8_MAX, INT8_MIN }; in ZTEST()
184 (0x04 << 5) | 1, in ZTEST()
185 (0x05 << 5) | 3, in ZTEST()
[all …]
/Zephyr-Core-3.5.0/drivers/ieee802154/
Dieee802154_cc1200_rf.h32 0x6F, /* SYNC3 */
33 0x4E,
34 0x90,
35 0x4E,
36 0xE5,
37 0x23,
38 0x47,
39 0x0B,
40 0x56,
41 0x19, /* 0x14 */
[all …]
/Zephyr-Core-3.5.0/subsys/net/ip/
D6lo_private.h16 #define NET_6LO_DISPATCH_IPV6 0x41 /* 01000001 */
17 #define NET_6LO_DISPATCH_BROADCAST 0x50 /* 01010000 */
18 #define NET_6LO_DISPATCH_IPHC 0x60 /* 01100000 */
19 #define NET_6LO_DISPATCH_MESH 0x80 /* 10xxxxxx */
20 #define NET_6LO_DISPATCH_FRAG1 0xC0 /* 11000xxx */
21 #define NET_6LO_DISPATCH_FRAGN 0xE0 /* 11100xxx */
23 #define NET_6LO_DISPATCH_IPHC_MASK 0xE0
32 #define NET_6LO_IPHC_TF_MASK (0x03 << NET_6LO_IPHC_TF_POS)
33 #define NET_6LO_IPHC_TF_00 (0x00 << NET_6LO_IPHC_TF_POS)
34 #define NET_6LO_IPHC_TF_01 (0x01 << NET_6LO_IPHC_TF_POS)
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/bmi323/
Dbmi323.h13 #define IMU_BOSCH_BMI323_REG_ACC_DATA_X (0x03)
14 #define IMU_BOSCH_BMI323_REG_ACC_DATA_Y (0x04)
15 #define IMU_BOSCH_BMI323_REG_ACC_DATA_Z (0x05)
17 #define IMU_BOSCH_BMI323_REG_GYRO_DATA_X (0x06)
18 #define IMU_BOSCH_BMI323_REG_GYRO_DATA_Y (0x07)
19 #define IMU_BOSCH_BMI323_REG_GYRO_DATA_Z (0x08)
21 #define IMU_BOSCH_BMI323_REG_TEMP_DATA (0x09)
23 #define IMU_BOSCH_BMI323_REG_FEATURE_IO0 (0x10)
25 #define IMU_BOSCH_BMI323_REG_FEATURE_IO0_MOTION_X_EN_OFFSET (0x03)
26 #define IMU_BOSCH_BMI323_REG_FEATURE_IO0_MOTION_X_EN_SIZE (0x01)
[all …]
/Zephyr-Core-3.5.0/dts/riscv/
Dvirt.dtsi16 #address-cells = < 0x01 >;
17 #size-cells = < 0x01 >;
22 bank-width = < 0x04 >;
23 reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >;
28 interrupts = < 0x0a 1 >;
30 clock-frequency = < 0x384000 >;
31 reg = < 0x10000000 0x100 >;
33 reg-shift = < 0 >;
37 #address-cells = < 0x01 >;
38 #size-cells = < 0x00 >;
[all …]
/Zephyr-Core-3.5.0/tests/subsys/jwt/src/
Djwt-test-cert.c10 0x30, 0x13, 0x31, 0x11, 0x30, 0x0F, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0C,
11 0x08, 0x6A, 0x77, 0x74, 0x2D, 0x74, 0x65, 0x73, 0x74,
14 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7,
15 0x0D, 0x01, 0x01,
16 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01, 0x0A, 0x02,
17 0x82, 0x01, 0x01,
18 0x00, 0xA6, 0x52, 0x98, 0xDF, 0x0E, 0x33, 0xD0, 0x69, 0x62, 0x32, 0xC4, 0x40,
19 0x7C, 0xEC, 0xBF,
20 0x9F, 0xA3, 0x35, 0x8A, 0x51, 0xCD, 0xED, 0x49, 0x99, 0xBE, 0xF8, 0x29, 0x3F,
21 0xD1, 0xD7, 0xA8,
[all …]
/Zephyr-Core-3.5.0/subsys/fb/
Dcfb_fonts.c20 0x00, 0x00,
21 0x00, 0x00,
22 0x00, 0x00,
23 0x00, 0x00,
24 0x00, 0x00,
25 0x00, 0x00,
26 0x00, 0x00,
27 0x00, 0x00,
28 0x00, 0x00,
29 0x00, 0x00,
[all …]
/Zephyr-Core-3.5.0/samples/net/mqtt_publisher/src/
Dtest_certs.h31 0x30, 0x82, 0x02, 0xfb, 0x30, 0x82, 0x01, 0xe3,
32 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x09, 0x00,
33 0xee, 0x10, 0x1f, 0xc1, 0xf2, 0x30, 0xe9, 0x11,
34 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86,
35 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30,
36 0x14, 0x31, 0x12, 0x30, 0x10, 0x06, 0x03, 0x55,
37 0x04, 0x03, 0x0c, 0x09, 0x6c, 0x6f, 0x63, 0x61,
38 0x6c, 0x68, 0x6f, 0x73, 0x74, 0x30, 0x1e, 0x17,
39 0x0d, 0x31, 0x37, 0x30, 0x36, 0x32, 0x36, 0x31,
40 0x30, 0x35, 0x36, 0x31, 0x30, 0x5a, 0x17, 0x0d,
[all …]
/Zephyr-Core-3.5.0/tests/net/ipv6_fragment/src/
Dmain.c36 static struct in6_addr my_addr1 = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
37 0, 0, 0, 0, 0, 0, 0, 0x1 } } };
40 static struct in6_addr my_addr2 = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
41 0, 0, 0, 0, 0, 0, 0, 0x2 } } };
44 static struct in6_addr ll_addr = { { { 0xfe, 0x80, 0x43, 0xb8, 0, 0, 0, 0,
45 0, 0, 0, 0xf2, 0xaa, 0x29, 0x02,
46 0x04 } } };
48 static uint8_t mac2_addr[] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x02 };
57 0x60, 0x00, 0x00, 0x00, 0x00, 0x36, 0x11, 0x3f, /* `....6.? */
58 0x20, 0x01, 0x0D, 0xB8, 0x00, 0x00, 0x00, 0x00,
[all …]
/Zephyr-Core-3.5.0/tests/drivers/uart/uart_async_api/boards/
Dnucleo_f207zg.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
Dnucleo_f429zi.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
Dnucleo_f767zi.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
Dnucleo_f746zg.overlay4 dmas = <&dma2 7 5 0x28440 0x03>,
5 <&dma2 2 5 0x28480 0x03>;
/Zephyr-Core-3.5.0/tests/bluetooth/host/data/bt_data_parse/src/
Dmain.c28 * - data.len set to 0
35 struct net_buf_simple *buf = NET_BUF_SIMPLE(0); in ZTEST()
39 zassert_equal(bt_data_parse_func_fake.call_count, 0); in ZTEST()
56 0x02, 0x01, 0x00, /* AD Structure 1 */ in ZTEST()
57 0x03, 0x02, 0x01, 0x00, /* AD Structure 2 */ in ZTEST()
58 /* Invalid length 0xff */ in ZTEST()
59 0xff, 0x03, 0x02, 0x01, /* AD Structure N */ in ZTEST()
60 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, /* AD Structure N + 1 */ in ZTEST()
88 0x02, 0x01, 0x00, /* AD Structure 1 */ in ZTEST()
89 0x03, 0x02, 0x01, 0x00, /* AD Structure 2 */ in ZTEST()
[all …]
/Zephyr-Core-3.5.0/subsys/net/lib/socks/
Dsocks_internal.h10 #define SOCKS5_PKT_MAGIC 0x05
11 #define SOCKS5_PKT_RSV 0x00
13 #define SOCKS5_AUTH_METHOD_NOAUTH 0x00
14 #define SOCKS5_AUTH_METHOD_GSSAPI 0x01
15 #define SOCKS5_AUTH_METHOD_USERPASS 0x02
16 #define SOCKS5_AUTH_METHOD_NONEG 0xFF
18 #define SOCKS5_CMD_CONNECT 0x01
19 #define SOCKS5_CMD_BIND 0x02
20 #define SOCKS5_CMD_UDP_ASSOCIATE 0x03
22 #define SOCKS5_ATYP_IPV4 0x01
[all …]
/Zephyr-Core-3.5.0/drivers/audio/
Dmpxxdtyy.c17 #define CHANNEL_MASK 0x55
20 0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
21 0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
22 0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
23 0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
24 0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
25 0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
26 0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
27 0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
28 0x08, 0x09, 0x08, 0x09, 0x0a, 0x0b, 0x0a, 0x0b,
[all …]
/Zephyr-Core-3.5.0/subsys/bluetooth/host/
Davdtp_internal.h12 #define A2DP_SRC_ROLE 0x00
13 #define A2DP_SNK_ROLE 0x01
16 #define BT_AVDTP_INT 0x00
17 #define BT_AVDTP_ACP 0x01
19 #define BT_L2CAP_PSM_AVDTP 0x0019
22 #define BT_AVDTP_PACKET_TYPE_SINGLE 0x00
23 #define BT_AVDTP_PACKET_TYPE_START 0x01
24 #define BT_AVDTP_PACKET_TYPE_CONTINUE 0x02
25 #define BT_AVDTP_PACKET_TYPE_END 0x03
28 #define BT_AVDTP_CMD 0x00
[all …]
/Zephyr-Core-3.5.0/tests/net/lib/dns_packet/src/
Dmain.c27 * Transaction ID: 0xda0f
30 static uint8_t query_ipv4[] = { 0xda, 0x0f, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00,
31 0x00, 0x00, 0x00, 0x00, 0x03, 0x77, 0x77, 0x77,
32 0x0d, 0x7a, 0x65, 0x70, 0x68, 0x79, 0x72, 0x70,
33 0x72, 0x6f, 0x6a, 0x65, 0x63, 0x74, 0x03, 0x6f,
34 0x72, 0x67, 0x00, 0x00, 0x01, 0x00, 0x01 };
43 0xda, 0x0f, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00,
44 0x00, 0x00, 0x00, 0x00, 0x06, 0x7a, 0x65, 0x70,
45 0x68, 0x79, 0x72, 0x05, 0x6c, 0x6f, 0x63, 0x61,
46 0x6c, 0x00, 0x00, 0x01, 0x00, 0x01,
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/icm42605/
Dicm42605_reg.h10 /* BANK 0 */
11 #define REG_DEVICE_CONFIG 0x11
12 #define REG_DRIVE_CONFIG 0x13
13 #define REG_INT_CONFIG 0x14
14 #define REG_FIFO_CONFIG 0x16
15 #define REG_TEMP_DATA1 0x1D
16 #define REG_TEMP_DATA0 0x1E
17 #define REG_ACCEL_DATA_X1 0x1F
18 #define REG_ACCEL_DATA_X0 0x20
19 #define REG_ACCEL_DATA_Y1 0x21
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/bmi270/
Dbmi270_config_file.h12 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x1a, 0x00, 0xc8, 0x2e, 0x00,
13 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0xc8, 0x2e,
14 0x00, 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0x90,
15 0x32, 0x21, 0x2e, 0x59, 0xf5, 0x10, 0x30, 0x21, 0x2e, 0x6a, 0xf5,
16 0x1a, 0x24, 0x22, 0x00, 0x80, 0x2e, 0x3b, 0x00, 0xc8, 0x2e, 0x44,
17 0x47, 0x22, 0x00, 0x37, 0x00, 0xa4, 0x00, 0xff, 0x0f, 0xd1, 0x00,
18 0x07, 0xad, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80,
19 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
20 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00,
21 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
[all …]
/Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/
Dnucleo_f746zg.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
11 slow@0 {
13 reg = <0>;
16 fast@0 {
18 reg = <0>;
Dnucleo_f767zi.overlay8 dmas = <&dma2 5 3 0x28440 0x03
9 &dma2 2 3 0x28480 0x03>;
11 slow@0 {
13 reg = <0>;
16 fast@0 {
18 reg = <0>;

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