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/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM33/
Dpartition_ARMCM33.h3 * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
10 * SPDX-License-Identifier: Apache-2.0
16 * www.apache.org/licenses/LICENSE-2.0
29 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
39 // <i> Value for SAU->CTRL register bit ENABLE
44 // <o> When SAU is disabled
46 // <1=> All Memory is Non-Secure
47 // <i> Value for SAU->CTRL register bit ALLNS
48 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM55/
Dpartition_ARMCM55.h3 * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
10 * SPDX-License-Identifier: Apache-2.0
16 * www.apache.org/licenses/LICENSE-2.0
29 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
39 // <i> Value for SAU->CTRL register bit ENABLE
44 // <o> When SAU is disabled
46 // <1=> All Memory is Non-Secure
47 // <i> Value for SAU->CTRL register bit ALLNS
48 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
59 // <i> - Secure and Non-Secure Callable
[all …]
/cmsis-dsp-latest/dsppp/RTE/Device/SSE_300_MPS3/
Dregions_V2M_MPS3_SSE_300_FVP.h5 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
17 // <o> Base address <0x0-0xFFFFFFFF:8>
21 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
34 // <o> Base address <0x0-0xFFFFFFFF:8>
38 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
51 // <o> Base address <0x0-0xFFFFFFFF:8>
55 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
68 // <o> Base address <0x0-0xFFFFFFFF:8>
72 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
85 // <o> Base address <0x0-0xFFFFFFFF:8>
[all …]
/cmsis-dsp-latest/PythonWrapper/cmsisdsp_pkg/src/
Dcmsisdsp_statistics.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
56 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_power_q31()
66 PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); in cmsis_arm_power_q31()
86 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_power_f32()
[all …]
Dcmsisdsp_support.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
46 if (self->instance) in arm_sort_instance_f32_dealloc()
49 PyMem_Free(self->instance); in arm_sort_instance_f32_dealloc()
52 Py_TYPE(self)->tp_free((PyObject*)self); in arm_sort_instance_f32_dealloc()
[all …]
Dcmsisdsp_window.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
61 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_welch_f32()
87 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_welch_f64()
114 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_bartlett_f32()
[all …]
Dcmsisdsp_complexf.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
62 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_cmplx_conj_f32()
75 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_cmplx_conj_f32()
95 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_cmplx_conj_q31()
[all …]
Dcmsisdsp_basic.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
130 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_mult_q7()
166 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_mult_q15()
202 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_mult_q31()
[all …]
Dcmsisdsp_quaternion.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
73 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_quaternion_product_f32()
106 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_quaternion_product_single_f32()
128 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_quaternion2rotation_f32()
[all …]
Dcmsisdsp_fastmath.c1 /* ----------------------------------------------------------------------
4 * Description: C code for the CMSIS-DSP Python wrapper
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
56 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_vlog_q15()
68 PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); in cmsis_arm_vlog_q15()
90 if (PyArg_ParseTuple(args,"O",&pSrc)) in cmsis_arm_vlog_q31()
[all …]
/cmsis-dsp-latest/Documentation/Doxygen/style_template/
Dnavtree.js6 Copyright (C) 1997-2020 by Dimitri van Heesch
33 return eval(n.replace(/\-/g,'_'));
46 return m ? uri.substring(i-6) : s;
51 return $(location).attr('hash').substring(1).replace(/[^\w\-]/g,'');
61 return $(location).attr('pathname').replace(/[^-A-Za-z0-9+&@#/%?=~_|!:,.;\(\)]/g, '');
76 if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) {
108 function createIndent(o,domNode,node,level) argument
110 var level=-1;
127 expandNode(o, node, false, false);
145 var pos, docContent = $('#doc-content');
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/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/SSE_300_MPS3/
Dregions_SSE_300_MPS3.h5 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
17 // <o> Base address <0x0-0xFFFFFFFF:8>
21 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
34 // <o> Base address <0x0-0xFFFFFFFF:8>
38 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
51 // <o> Base address <0x0-0xFFFFFFFF:8>
55 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
68 // <o> Base address <0x0-0xFFFFFFFF:8>
72 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
85 // <o> Base address <0x0-0xFFFFFFFF:8>
[all …]
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/SSE_310_MPS3/
Dregions_SSE_310_MPS3.h5 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
17 // <o> Base address <0x0-0xFFFFFFFF:8>
21 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
34 // <o> Base address <0x0-0xFFFFFFFF:8>
38 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
51 // <o> Base address <0x0-0xFFFFFFFF:8>
55 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
68 // <o> Base address <0x0-0xFFFFFFFF:8>
72 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
85 // <o> Base address <0x0-0xFFFFFFFF:8>
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-310-MPS3/
Dregions_SSE-310-MPS3.h5 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
17 // <o> Base address <0x0-0xFFFFFFFF:8>
21 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
34 // <o> Base address <0x0-0xFFFFFFFF:8>
38 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
51 // <o> Base address <0x0-0xFFFFFFFF:8>
55 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
68 // <o> Base address <0x0-0xFFFFFFFF:8>
72 // <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
85 // <o> Base address <0x0-0xFFFFFFFF:8>
[all …]
Dcorstone310_mps3_s.ld2 ; * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
8 ; * http://www.apache.org/licenses/LICENSE-2.0
21 /* This file will be run trough the pre-processor. */
45 __Vectors_Size = __Vectors_End - __Vectors;
55 *crtbegin.o(.ctors)
56 *crtbegin?.o(.ctors)
57 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
62 *crtbegin.o(.dtors)
63 *crtbegin?.o(.dtors)
64 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA5/
DARMCA5.ld29 *crtbegin.o(.ctors)
30 *crtbegin?.o(.ctors)
31 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
36 *crtbegin.o(.dtors)
37 *crtbegin?.o(.dtors)
38 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
68 LONG (__data_end__ - __data_start__)
77 LONG (__bss_end__ - __bss_start__)
149 …. = ORIGIN(RAM) + LENGTH(RAM) - 0x00002000 - 0x00000100 - 0x00000100 - 0x00000100 - 0x00000100 - 0…
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA7/
DARMCA7.ld29 *crtbegin.o(.ctors)
30 *crtbegin?.o(.ctors)
31 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
36 *crtbegin.o(.dtors)
37 *crtbegin?.o(.dtors)
38 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
68 LONG (__data_end__ - __data_start__)
77 LONG (__bss_end__ - __bss_start__)
149 …. = ORIGIN(RAM) + LENGTH(RAM) - 0x00002000 - 0x00000100 - 0x00000100 - 0x00000100 - 0x00000100 - 0…
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA9/
DARMCA9.ld29 *crtbegin.o(.ctors)
30 *crtbegin?.o(.ctors)
31 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
36 *crtbegin.o(.dtors)
37 *crtbegin?.o(.dtors)
38 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
68 LONG (__data_end__ - __data_start__)
77 LONG (__bss_end__ - __bss_start__)
149 …. = ORIGIN(RAM) + LENGTH(RAM) - 0x00002000 - 0x00000100 - 0x00000100 - 0x00000100 - 0x00000100 - 0…
/cmsis-dsp-latest/dsppp/RTE/Device/SSE-300-MPS3/
Dlinker_SSE300MPS3_secure.ld2 ; * Copyright (c) 2009-2023 Arm Limited
8 ; * http://www.apache.org/licenses/LICENSE-2.0
18 /* This file will be run trough the pre-processor. */
75 __Vectors_Size = __Vectors_End - __Vectors;
85 *crtbegin.o(.ctors)
86 *crtbegin?.o(.ctors)
87 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
92 *crtbegin.o(.dtors)
93 *crtbegin?.o(.dtors)
94 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
[all …]
Dlinker_SSE300MPS3_secure.ld.base@1.0.02 ; * Copyright (c) 2009-2023 Arm Limited
8 ; * http://www.apache.org/licenses/LICENSE-2.0
18 /* This file will be run trough the pre-processor. */
75 __Vectors_Size = __Vectors_End - __Vectors;
85 *crtbegin.o(.ctors)
86 *crtbegin?.o(.ctors)
87 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
92 *crtbegin.o(.dtors)
93 *crtbegin?.o(.dtors)
94 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/
Dlinker_SSE300MPS3_secure.ld2 ; * Copyright (c) 2009-2023 Arm Limited
8 ; * http://www.apache.org/licenses/LICENSE-2.0
18 /* This file will be run trough the pre-processor. */
75 __Vectors_Size = __Vectors_End - __Vectors;
85 *crtbegin.o(.ctors)
86 *crtbegin?.o(.ctors)
87 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
92 *crtbegin.o(.dtors)
93 *crtbegin?.o(.dtors)
94 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM0P/
DARMCM0plus_gcc.ld2 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
5 /*---------------------- Flash Configuration ----------------------------------
7 <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
8 <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
10 -----------------------------------------------------------------------------*/
14 /*--------------------- Embedded RAM Configuration ----------------------------
16 <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
17 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
19 -----------------------------------------------------------------------------*/
23 /*--------------------- Stack / Heap Configuration ----------------------------
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM4/
DARMCM4_gcc.ld2 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
5 /*---------------------- Flash Configuration ----------------------------------
7 <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
8 <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
10 -----------------------------------------------------------------------------*/
14 /*--------------------- Embedded RAM Configuration ----------------------------
16 <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
17 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
19 -----------------------------------------------------------------------------*/
23 /*--------------------- Stack / Heap Configuration ----------------------------
[all …]
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM0P/
DARMCM0plus_gcc.ld2 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
5 /*---------------------- Flash Configuration ----------------------------------
7 <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
8 <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
10 -----------------------------------------------------------------------------*/
14 /*--------------------- Embedded RAM Configuration ----------------------------
16 <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
17 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
19 -----------------------------------------------------------------------------*/
23 /*--------------------- Stack / Heap Configuration ----------------------------
[all …]
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM4/
DARMCM4_gcc.ld2 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
5 /*---------------------- Flash Configuration ----------------------------------
7 <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
8 <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
10 -----------------------------------------------------------------------------*/
14 /*--------------------- Embedded RAM Configuration ----------------------------
16 <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
17 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
19 -----------------------------------------------------------------------------*/
23 /*--------------------- Stack / Heap Configuration ----------------------------
[all …]

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