1 /*
2 * Copyright (c) 2023 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #define DT_DRV_COMPAT ite_it8xxx2_gpio_v2
9
10 #include <chip_chipregs.h>
11 #include <errno.h>
12 #include <soc.h>
13 #include <soc_dt.h>
14 #include <string.h>
15 #include <zephyr/device.h>
16 #include <zephyr/drivers/gpio.h>
17 #include <zephyr/drivers/gpio/gpio_utils.h>
18 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
19 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
20 #include <zephyr/init.h>
21 #include <zephyr/irq.h>
22 #include <zephyr/kernel.h>
23 #include <zephyr/spinlock.h>
24 #include <zephyr/sys/util.h>
25 #include <zephyr/types.h>
26 #include <zephyr/logging/log.h>
27
28 LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
29
30 #define ITE_GPIO_MAX_PINS 8
31
32 /*
33 * Structure gpio_ite_cfg is about the setting of GPIO
34 * this config will be used at initial time
35 */
36 struct gpio_ite_cfg {
37 /* gpio_driver_config needs to be first */
38 struct gpio_driver_config common;
39 /* GPIO port data register (bit mapping to pin) */
40 uintptr_t reg_gpdr;
41 /* GPIO port data mirror register (bit mapping to pin) */
42 uintptr_t reg_gpdmr;
43 /* GPIO port output type register (bit mapping to pin) */
44 uintptr_t reg_gpotr;
45 /* GPIO port 1.8V select register (bit mapping to pin) */
46 uintptr_t reg_p18scr;
47 /* GPIO port control register (byte mapping to pin) */
48 uintptr_t reg_gpcr;
49 /* Wake up control base register */
50 uintptr_t wuc_base[8];
51 /* Wake up control mask */
52 uint8_t wuc_mask[8];
53 /* GPIO's irq */
54 uint8_t gpio_irq[8];
55 /* Support input voltage selection */
56 uint8_t has_volt_sel[8];
57 /* Number of pins per group of GPIO */
58 uint8_t num_pins;
59 /* gpioksi, gpioksoh and gpioksol extended setting */
60 bool kbs_ctrl;
61 };
62
63 /* Structure gpio_ite_data is about callback function */
64 struct gpio_ite_data {
65 struct gpio_driver_data common;
66 sys_slist_t callbacks;
67 uint8_t volt_default_set;
68 struct k_spinlock lock;
69 uint8_t level_isr_high;
70 uint8_t level_isr_low;
71 const struct device *instance;
72 struct k_work interrupt_worker;
73 };
74
75 /**
76 * Driver functions
77 */
gpio_ite_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)78 static int gpio_ite_configure(const struct device *dev,
79 gpio_pin_t pin,
80 gpio_flags_t flags)
81 {
82 const struct gpio_ite_cfg *gpio_config = dev->config;
83 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
84 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
85 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
86 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
87 struct gpio_ite_data *data = dev->data;
88 uint8_t mask = BIT(pin);
89 int rc = 0;
90
91 /* Don't support "open source" mode */
92 if (((flags & GPIO_SINGLE_ENDED) != 0) &&
93 ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
94 return -ENOTSUP;
95 }
96
97 k_spinlock_key_t key = k_spin_lock(&data->lock);
98 if (flags == GPIO_DISCONNECTED) {
99 ECREG(reg_gpcr) = GPCR_PORT_PIN_MODE_TRISTATE;
100 /*
101 * Since not all GPIOs can be to configured as tri-state,
102 * prompt error if pin doesn't support the flag.
103 */
104 if (ECREG(reg_gpcr) != GPCR_PORT_PIN_MODE_TRISTATE) {
105 /* Go back to default setting (input) */
106 ECREG(reg_gpcr) = GPCR_PORT_PIN_MODE_INPUT;
107 LOG_ERR("Cannot config the node-gpio@%x, pin=%d as tri-state",
108 (uint32_t)reg_gpdr, pin);
109 rc = -ENOTSUP;
110 goto unlock_and_return;
111 }
112 /*
113 * The following configuration isn't necessary because the pin
114 * was configured as disconnected.
115 */
116 rc = 0;
117 goto unlock_and_return;
118 }
119
120 /*
121 * Select open drain first, so that we don't glitch the signal
122 * when changing the line to an output.
123 */
124 if (flags & GPIO_OPEN_DRAIN) {
125 ECREG(reg_gpotr) |= mask;
126 } else {
127 ECREG(reg_gpotr) &= ~mask;
128 }
129
130 /* 1.8V or 3.3V */
131 if (gpio_config->has_volt_sel[pin]) {
132 gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
133
134 if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
135 __ASSERT(!(flags & GPIO_PULL_UP),
136 "Don't enable internal pullup if 1.8V voltage is used");
137 ECREG(reg_p18scr) |= mask;
138 data->volt_default_set &= ~mask;
139 } else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3) {
140 ECREG(reg_p18scr) &= ~mask;
141 /*
142 * A variable is needed to store the difference between
143 * 3.3V and default so that the flag can be distinguished
144 * between the two in gpio_ite_get_config.
145 */
146 data->volt_default_set &= ~mask;
147 } else if (volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
148 ECREG(reg_p18scr) &= ~mask;
149 data->volt_default_set |= mask;
150 } else {
151 rc = -EINVAL;
152 goto unlock_and_return;
153 }
154 }
155
156 /* If output, set level before changing type to an output. */
157 if (flags & GPIO_OUTPUT) {
158 if (flags & GPIO_OUTPUT_INIT_HIGH) {
159 ECREG(reg_gpdr) |= mask;
160 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
161 ECREG(reg_gpdr) &= ~mask;
162 }
163 }
164
165 /* Set input or output. */
166 if (gpio_config->kbs_ctrl) {
167 /* Handle keyboard scan controller */
168 uint8_t ksxgctrlr = ECREG(reg_gpcr);
169
170 ksxgctrlr |= KSIX_KSOX_KBS_GPIO_MODE;
171 if (flags & GPIO_OUTPUT) {
172 ksxgctrlr |= KSIX_KSOX_GPIO_OUTPUT;
173 } else {
174 ksxgctrlr &= ~KSIX_KSOX_GPIO_OUTPUT;
175 }
176 ECREG(reg_gpcr) = ksxgctrlr;
177 } else {
178 /* Handle regular GPIO controller */
179 if (flags & GPIO_OUTPUT) {
180 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_OUTPUT) &
181 ~GPCR_PORT_PIN_MODE_INPUT;
182 } else {
183 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_INPUT) &
184 ~GPCR_PORT_PIN_MODE_OUTPUT;
185 }
186 }
187
188 /* Handle pullup / pulldown */
189 if (gpio_config->kbs_ctrl) {
190 /* Handle keyboard scan controller */
191 uint8_t ksxgctrlr = ECREG(reg_gpcr);
192
193 if (flags & GPIO_PULL_UP) {
194 ksxgctrlr = (ksxgctrlr | KSIX_KSOX_GPIO_PULLUP) &
195 ~KSIX_KSOX_GPIO_PULLDOWN;
196 } else if (flags & GPIO_PULL_DOWN) {
197 ksxgctrlr = (ksxgctrlr | KSIX_KSOX_GPIO_PULLDOWN) &
198 ~KSIX_KSOX_GPIO_PULLUP;
199 } else {
200 /* No pull up/down */
201 ksxgctrlr &= ~(KSIX_KSOX_GPIO_PULLUP | KSIX_KSOX_GPIO_PULLDOWN);
202 }
203 ECREG(reg_gpcr) = ksxgctrlr;
204 } else {
205 /* Handle regular GPIO controller */
206 if (flags & GPIO_PULL_UP) {
207 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_PULLUP) &
208 ~GPCR_PORT_PIN_MODE_PULLDOWN;
209 } else if (flags & GPIO_PULL_DOWN) {
210 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_PULLDOWN) &
211 ~GPCR_PORT_PIN_MODE_PULLUP;
212 } else {
213 /* No pull up/down */
214 ECREG(reg_gpcr) &= ~(GPCR_PORT_PIN_MODE_PULLUP |
215 GPCR_PORT_PIN_MODE_PULLDOWN);
216 }
217 }
218
219 unlock_and_return:
220 k_spin_unlock(&data->lock, key);
221 return rc;
222 }
223
224 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_ite_get_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t * out_flags)225 static int gpio_ite_get_config(const struct device *dev,
226 gpio_pin_t pin,
227 gpio_flags_t *out_flags)
228 {
229 const struct gpio_ite_cfg *gpio_config = dev->config;
230 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
231 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
232 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
233 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
234 struct gpio_ite_data *data = dev->data;
235 uint8_t mask = BIT(pin);
236 gpio_flags_t flags = 0;
237
238 k_spinlock_key_t key = k_spin_lock(&data->lock);
239 /* push-pull or open-drain */
240 if (ECREG(reg_gpotr) & mask) {
241 flags |= GPIO_OPEN_DRAIN;
242 }
243
244 /* 1.8V or 3.3V */
245 if (gpio_config->has_volt_sel[pin]) {
246 if (data->volt_default_set & mask) {
247 flags |= IT8XXX2_GPIO_VOLTAGE_DEFAULT;
248 } else {
249 if (ECREG(reg_p18scr) & mask) {
250 flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
251 } else {
252 flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
253 }
254 }
255 }
256
257 /* set input or output. */
258 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_OUTPUT) {
259 flags |= GPIO_OUTPUT;
260
261 /* set level */
262 if (ECREG(reg_gpdr) & mask) {
263 flags |= GPIO_OUTPUT_HIGH;
264 } else {
265 flags |= GPIO_OUTPUT_LOW;
266 }
267 }
268
269 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_INPUT) {
270 flags |= GPIO_INPUT;
271
272 /* pullup / pulldown */
273 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_PULLUP) {
274 flags |= GPIO_PULL_UP;
275 }
276
277 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_PULLDOWN) {
278 flags |= GPIO_PULL_DOWN;
279 }
280 }
281
282 *out_flags = flags;
283 k_spin_unlock(&data->lock, key);
284
285 return 0;
286 }
287 #endif
288
gpio_ite_port_get_raw(const struct device * dev,gpio_port_value_t * value)289 static int gpio_ite_port_get_raw(const struct device *dev,
290 gpio_port_value_t *value)
291 {
292 const struct gpio_ite_cfg *gpio_config = dev->config;
293 volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
294
295 /* Get raw bits of GPIO mirror register */
296 *value = ECREG(reg_gpdmr);
297
298 return 0;
299 }
300
gpio_ite_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)301 static int gpio_ite_port_set_masked_raw(const struct device *dev,
302 gpio_port_pins_t mask,
303 gpio_port_value_t value)
304 {
305 const struct gpio_ite_cfg *gpio_config = dev->config;
306 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
307 uint8_t masked_value = value & mask;
308 struct gpio_ite_data *data = dev->data;
309 k_spinlock_key_t key = k_spin_lock(&data->lock);
310 uint8_t out = ECREG(reg_gpdr);
311
312 ECREG(reg_gpdr) = ((out & ~mask) | masked_value);
313 k_spin_unlock(&data->lock, key);
314
315 return 0;
316 }
317
gpio_ite_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)318 static int gpio_ite_port_set_bits_raw(const struct device *dev,
319 gpio_port_pins_t pins)
320 {
321 const struct gpio_ite_cfg *gpio_config = dev->config;
322 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
323 struct gpio_ite_data *data = dev->data;
324
325 k_spinlock_key_t key = k_spin_lock(&data->lock);
326 /* Set raw bits of GPIO data register */
327 ECREG(reg_gpdr) |= pins;
328 k_spin_unlock(&data->lock, key);
329
330 return 0;
331 }
332
gpio_ite_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)333 static int gpio_ite_port_clear_bits_raw(const struct device *dev,
334 gpio_port_pins_t pins)
335 {
336 const struct gpio_ite_cfg *gpio_config = dev->config;
337 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
338 struct gpio_ite_data *data = dev->data;
339
340 k_spinlock_key_t key = k_spin_lock(&data->lock);
341 /* Clear raw bits of GPIO data register */
342 ECREG(reg_gpdr) &= ~pins;
343 k_spin_unlock(&data->lock, key);
344
345 return 0;
346 }
347
gpio_ite_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)348 static int gpio_ite_port_toggle_bits(const struct device *dev,
349 gpio_port_pins_t pins)
350 {
351 const struct gpio_ite_cfg *gpio_config = dev->config;
352 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
353 struct gpio_ite_data *data = dev->data;
354
355 k_spinlock_key_t key = k_spin_lock(&data->lock);
356 /* Toggle raw bits of GPIO data register */
357 ECREG(reg_gpdr) ^= pins;
358 k_spin_unlock(&data->lock, key);
359
360 return 0;
361 }
362
gpio_ite_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)363 static int gpio_ite_manage_callback(const struct device *dev,
364 struct gpio_callback *callback,
365 bool set)
366 {
367 struct gpio_ite_data *data = dev->data;
368
369 k_spinlock_key_t key = k_spin_lock(&data->lock);
370 int rc = gpio_manage_callback(&data->callbacks, callback, set);
371
372 k_spin_unlock(&data->lock, key);
373 return rc;
374 }
375
gpio_ite_isr(const void * arg)376 static void gpio_ite_isr(const void *arg)
377 {
378 const struct device *dev = arg;
379 const struct gpio_ite_cfg *gpio_config = dev->config;
380 struct gpio_ite_data *data = dev->data;
381 uint8_t irq = ite_intc_get_irq_num();
382 uint8_t num_pins = gpio_config->num_pins;
383 uint8_t pin;
384
385 for (pin = 0; pin < num_pins; pin++) {
386 if (irq == gpio_config->gpio_irq[pin]) {
387 volatile uint8_t *reg_base =
388 (uint8_t *)gpio_config->wuc_base[pin];
389 volatile uint8_t *reg_wuesr = reg_base + 1;
390 uint8_t wuc_mask = gpio_config->wuc_mask[pin];
391
392 /* Should be safe even without spinlock. */
393 /* Clear the WUC status register. */
394 ECREG(reg_wuesr) = wuc_mask;
395 /* The callbacks are user code, and therefore should
396 * not hold the lock.
397 */
398 gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
399
400 break;
401 }
402 }
403 /* Reschedule worker */
404 k_work_submit(&data->interrupt_worker);
405 }
406
gpio_ite_interrupt_worker(struct k_work * work)407 static void gpio_ite_interrupt_worker(struct k_work *work)
408 {
409 struct gpio_ite_data * const data = CONTAINER_OF(
410 work, struct gpio_ite_data, interrupt_worker);
411 gpio_port_value_t value;
412 gpio_port_value_t triggered_int;
413
414 gpio_ite_port_get_raw(data->instance, &value);
415
416 k_spinlock_key_t key = k_spin_lock(&data->lock);
417
418 triggered_int = (value & data->level_isr_high) | (~value & data->level_isr_low);
419 k_spin_unlock(&data->lock, key);
420
421 if (triggered_int != 0) {
422 gpio_fire_callbacks(&data->callbacks, data->instance,
423 triggered_int);
424 /* Reschedule worker */
425 k_work_submit(&data->interrupt_worker);
426 }
427 }
428
gpio_ite_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)429 static int gpio_ite_pin_interrupt_configure(const struct device *dev,
430 gpio_pin_t pin,
431 enum gpio_int_mode mode,
432 enum gpio_int_trig trig)
433 {
434 const struct gpio_ite_cfg *gpio_config = dev->config;
435 uint8_t gpio_irq = gpio_config->gpio_irq[pin];
436 struct gpio_ite_data *data = dev->data;
437
438 #ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
439 if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
440 #else
441 if (mode == GPIO_INT_MODE_DISABLED) {
442 #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
443 /* Disable GPIO interrupt */
444 irq_disable(gpio_irq);
445 return 0;
446 #ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
447 } else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
448 /* Only enable GPIO interrupt */
449 irq_enable(gpio_irq);
450 return 0;
451 #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
452 }
453
454 /* Disable irq before configuring it */
455 irq_disable(gpio_irq);
456
457 if (trig & GPIO_INT_TRIG_BOTH) {
458 volatile uint8_t *reg_base = (uint8_t *)gpio_config->wuc_base[pin];
459 volatile uint8_t *reg_wuemr = reg_base;
460 volatile uint8_t *reg_wuesr = reg_base + 1;
461 volatile uint8_t *reg_wubemr = reg_base + 3;
462 uint8_t wuc_mask = gpio_config->wuc_mask[pin];
463
464 k_spinlock_key_t key = k_spin_lock(&data->lock);
465
466 /* Set both edges interrupt. */
467 if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
468 ECREG(reg_wubemr) |= wuc_mask;
469 } else {
470 ECREG(reg_wubemr) &= ~wuc_mask;
471 }
472
473 if (trig & GPIO_INT_TRIG_LOW) {
474 ECREG(reg_wuemr) |= wuc_mask;
475 } else {
476 ECREG(reg_wuemr) &= ~wuc_mask;
477 }
478
479 if (mode == GPIO_INT_MODE_LEVEL) {
480 if (trig & GPIO_INT_TRIG_LOW) {
481 data->level_isr_low |= BIT(pin);
482 data->level_isr_high &= ~BIT(pin);
483 } else {
484 data->level_isr_low &= ~BIT(pin);
485 data->level_isr_high |= BIT(pin);
486 }
487 } else {
488 data->level_isr_low &= ~BIT(pin);
489 data->level_isr_high &= ~BIT(pin);
490 }
491 /*
492 * Always write 1 to clear the WUC status register after
493 * modifying edge mode selection register (WUBEMR and WUEMR).
494 */
495 ECREG(reg_wuesr) = wuc_mask;
496 k_spin_unlock(&data->lock, key);
497 }
498
499 /* Enable GPIO interrupt */
500 irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
501 irq_enable(gpio_irq);
502 k_work_submit(&data->interrupt_worker);
503
504 return 0;
505 }
506
507 static DEVICE_API(gpio, gpio_ite_driver_api) = {
508 .pin_configure = gpio_ite_configure,
509 #ifdef CONFIG_GPIO_GET_CONFIG
510 .pin_get_config = gpio_ite_get_config,
511 #endif
512 .port_get_raw = gpio_ite_port_get_raw,
513 .port_set_masked_raw = gpio_ite_port_set_masked_raw,
514 .port_set_bits_raw = gpio_ite_port_set_bits_raw,
515 .port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
516 .port_toggle_bits = gpio_ite_port_toggle_bits,
517 .pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
518 .manage_callback = gpio_ite_manage_callback,
519 };
520
521 static int gpio_ite_init(const struct device *dev)
522 {
523 struct gpio_ite_data *data = dev->data;
524 k_spinlock_key_t key = k_spin_lock(&data->lock);
525
526 data->instance = dev;
527 k_work_init(&data->interrupt_worker,
528 gpio_ite_interrupt_worker);
529 k_spin_unlock(&data->lock, key);
530
531 return 0;
532 }
533
534 #define GPIO_ITE_DEV_CFG_DATA(inst) \
535 BUILD_ASSERT(DT_INST_PROP(inst, ngpios) <= ITE_GPIO_MAX_PINS, \
536 "The maximum number of pins per port is 8."); \
537 static struct gpio_ite_data gpio_ite_data_##inst; \
538 static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
539 .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst)}, \
540 .reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
541 .reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
542 .reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
543 .reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
544 .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4), \
545 .wuc_base = DT_INST_PROP_OR(inst, wuc_base, {0}), \
546 .wuc_mask = DT_INST_PROP_OR(inst, wuc_mask, {0}), \
547 .gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst), \
548 .has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}), \
549 .num_pins = DT_INST_PROP(inst, ngpios), \
550 .kbs_ctrl = DT_INST_PROP_OR(inst, keyboard_controller, 0), \
551 }; \
552 DEVICE_DT_INST_DEFINE(inst, gpio_ite_init, NULL, &gpio_ite_data_##inst, \
553 &gpio_ite_cfg_##inst, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
554 &gpio_ite_driver_api);
555
556 DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
557
558 #ifdef CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
559 static int gpio_it8xxx2_init_set(void)
560 {
561 const struct device *const gpiok = DEVICE_DT_GET(DT_NODELABEL(gpiok));
562 const struct device *const gpiol = DEVICE_DT_GET(DT_NODELABEL(gpiol));
563
564 for (int i = 0; i < 8; i++) {
565 gpio_pin_configure(gpiok, i, GPIO_INPUT | GPIO_PULL_DOWN);
566 gpio_pin_configure(gpiol, i, GPIO_INPUT | GPIO_PULL_DOWN);
567 }
568
569 return 0;
570 }
571 SYS_INIT(gpio_it8xxx2_init_set, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
572 #endif /* CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN */
573
