1/*
2 * Copyright 2022-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
10#include <dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
12#include <dt-bindings/adc/nxp,gau-adc.h>
13#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
14#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15
16/ {
17	chosen {
18		zephyr,entropy = &trng;
19		zephyr,nbu = &nbu;
20		zephyr,bt-hci = &hci;
21		zephyr,hdlc-rcp-if = &hdlc_rcp_if;
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			compatible = "arm,cortex-m33f";
30			reg = <0>;
31			#address-cells = <1>;
32			#size-cells = <1>;
33			cpu-power-states = <&idle &suspend>;
34
35			mpu: mpu@e000ed90 {
36				compatible = "arm,armv8m-mpu";
37				reg = <0xe000ed90 0x40>;
38			};
39		};
40
41		power-states {
42			/* Idle mode maps to Power Mode 1 */
43			idle: idle {
44				compatible = "zephyr,power-state";
45				power-state-name = "runtime-idle";
46				min-residency-us = <0>;
47				exit-latency-us = <0>;
48			};
49			/* Suspend mode maps to Power Mode 2 */
50			suspend: suspend {
51				compatible = "nxp,pdcfg-power", "zephyr,power-state";
52				power-state-name = "suspend-to-idle";
53				min-residency-us = <500>;
54				exit-latency-us = <120>;
55				deep-sleep-config = <0x180000>,
56							<0x0>,
57							<0x4>,
58							<0x100>,
59							<0x0>;
60			};
61		};
62	};
63
64	smu1: sram@41380000 {
65		ranges = <0x0 0x41380000 DT_SIZE_K(510)>;
66	};
67
68	smu2: sram@443C0000 {
69		ranges = <0x0 0x443C0000 DT_SIZE_K(140)>;
70	};
71
72};
73
74&sram {
75	#address-cells = <1>;
76	#size-cells = <1>;
77
78	/* RW6XX SRAM can be access by either code or data bus, determined
79	 * by the address used to access the memory.
80	 * Applications can override the reg properties of either
81	 * sram_data or sram_code nodes to change the balance of SRAM access partitioning.
82	 */
83	sram_data: memory@40000 {
84		compatible = "mmio-sram";
85		reg = <0x40000 DT_SIZE_K(960)>;
86	};
87
88	sram_code: memory@0 {
89		compatible = "mmio-sram";
90		reg = <0x00000000 DT_SIZE_K(256)>;
91	};
92};
93
94&smu1 {
95	#address-cells = <1>;
96	#size-cells = <1>;
97
98	smu1_data: memory@0 {
99		compatible = "zephyr,memory-region","mmio-sram";
100		reg = <0x0 DT_SIZE_K(510)>;
101		zephyr,memory-region = "SMU1";
102		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
103	};
104};
105
106&smu2 {
107	#address-cells = <1>;
108	#size-cells = <1>;
109
110	smu2_data: memory@0 {
111		compatible = "zephyr,memory-region","mmio-sram";
112		reg = <0x0 DT_SIZE_K(140)>;
113		zephyr,memory-region = "SMU2";
114		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
115	};
116};
117
118&peripheral {
119	#address-cells = <1>;
120	#size-cells = <1>;
121
122	flexspi: spi@134000 {
123		reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
124	};
125
126	clkctl0: clkctl@1000 {
127		/* FIXME This chip does NOT have a syscon */
128		compatible = "nxp,lpc-syscon";
129		reg = <0x1000 0x1000>;
130		#clock-cells = <1>;
131	};
132
133	pinctrl: mci_iomux@4000 {
134		compatible = "nxp,mci-io-mux";
135		reg = <0x4000 0x1000>;
136		status = "okay";
137	};
138
139	clkctl1: clkctl@21000 {
140		/* FIXME This chip does NOT have a syscon */
141		compatible = "nxp,lpc-syscon";
142		reg = <0x21000 0x1000>;
143		#clock-cells = <1>;
144	};
145
146	rstctl0: reset@0 {
147		compatible = "nxp,rstctl";
148		reg = <0x0 0x80>;
149		#reset-cells = <1>;
150	};
151
152	rstctl1: reset@20000 {
153		compatible = "nxp,rstctl";
154		reg = <0x20000 0x80>;
155		#reset-cells = <1>;
156	};
157
158	pmu: pmu@31000 {
159		reg = <0x31000 0x130>;
160		compatible = "nxp,rw-pmu";
161		pin0: pin0 {
162			compatible = "nxp,aon-wakeup-pin";
163			interrupts = <100 0>;
164			status = "disabled";
165		};
166		pin1: pin1 {
167			compatible = "nxp,aon-wakeup-pin";
168			interrupts = <101 0>;
169			status = "disabled";
170		};
171	};
172
173	trng: random@14000 {
174		compatible = "nxp,kinetis-trng";
175		reg = <0x14000 0x1000>;
176		status = "okay";
177		interrupts = <123 0>;
178	};
179
180	wwdt: watchdog@e000 {
181		compatible = "nxp,lpc-wwdt";
182		reg = <0xe000 0x1000>;
183		interrupts = <0 0>;
184		status = "disabled";
185		clk-divider = <1>;
186	};
187
188	hsgpio: hsgpio@100000 {
189		compatible = "nxp,lpc-gpio";
190		reg = <0x100000 0x4000>;
191		#address-cells = <1>;
192		#size-cells = <0>;
193
194		hsgpio0: gpio@0 {
195			compatible = "nxp,lpc-gpio-port";
196			gpio-controller;
197			#gpio-cells = <2>;
198			reg = <0>;
199			int-source = "pint";
200		};
201
202		hsgpio1: gpio@1 {
203			compatible = "nxp,lpc-gpio-port";
204			gpio-controller;
205			#gpio-cells = <2>;
206			reg = <1>;
207			int-source = "pint";
208		};
209	};
210
211	usb_otg: usbotg@145000 {
212		compatible = "nxp,ehci";
213		reg = <0x145000 0x200>;
214		interrupts = <50 1>;
215		interrupt-names = "usb_otg";
216		num-bidir-endpoints = <8>;
217		status = "disabled";
218	};
219
220	flexcomm0: flexcomm@106000 {
221		compatible = "nxp,lpc-flexcomm";
222		reg = <0x106000 0x1000>;
223		interrupts = <14 0>;
224		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
225		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
226		dmas = <&dma0 0>, <&dma0 1>;
227		dma-names = "rx", "tx";
228		status = "disabled";
229	};
230
231	flexcomm1: flexcomm@107000 {
232		compatible = "nxp,lpc-flexcomm";
233		reg = <0x107000 0x1000>;
234		interrupts = <15 0>;
235		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
236		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
237		dmas = <&dma0 2>, <&dma0 3>;
238		dma-names = "rx", "tx";
239		status = "disabled";
240	};
241
242	flexcomm2: flexcomm@108000 {
243		compatible = "nxp,lpc-flexcomm";
244		reg = <0x108000 0x1000>;
245		interrupts = <16 0>;
246		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
247		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
248		dmas = <&dma0 4>, <&dma0 5>;
249		dma-names = "rx", "tx";
250		status = "disabled";
251	};
252
253	flexcomm3: flexcomm@109000 {
254		compatible = "nxp,lpc-flexcomm";
255		reg = <0x109000 0x1000>;
256		interrupts = <17 0>;
257		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
258		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
259		dmas = <&dma0 6>, <&dma0 7>;
260		dma-names = "rx", "tx";
261		status = "disabled";
262	};
263
264	flexcomm14: flexcom@126000 {
265		compatible = "nxp,lpc-flexcomm";
266		reg = <0x126000 0x2000>;
267		interrupts = <20 0>;
268		clocks = <&clkctl1 MCUX_FLEXCOMM14_CLK>;
269		resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
270		dmas = <&dma0 26>, <&dma0 27>;
271		dma-names = "rx", "tx";
272		status = "disabled";
273	};
274
275	aon_soc_ctrl: aon_soc_ctrl@5000800 {
276		compatible = "nxp,rw-soc-ctrl";
277		reg = <0x5000800 0x1000>;
278		status = "okay";
279	};
280
281	soc_ctrl: soc_ctrl@5001000 {
282		compatible = "nxp,rw-soc-ctrl";
283		reg = <0x5001000 0x1000>;
284		status = "okay";
285	};
286
287	pint: pint@25000 {
288		compatible = "nxp,pint";
289		reg = <0x25000 0x1000>;
290		interrupt-controller;
291		#interrupt-cells = <1>;
292		#address-cells = <0>;
293		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
294			<35 2>, <36 2>, <37 2>, <38 2>;
295		num-lines = <8>;
296		num-inputs = <64>;
297	};
298
299	imu: nxp_wifi {
300		compatible = "nxp,wifi";
301		/* first index is the imu interrupt, the second is the wakeup done interrupt */
302		interrupts = <72 2>, <64 2>;
303	};
304
305	dma0: dma-controller@104000 {
306		compatible = "nxp,lpc-dma";
307		reg = <0x104000 0x1000>;
308		interrupts = <1 0>;
309		status = "disabled";
310		#dma-cells = <1>;
311		dma-channels = <33>;
312	};
313
314	lcdic: lcdic@128000 {
315		compatible = "nxp,lcdic";
316		reg = <0x128000 0x52>;
317		interrupts = <61 0>;
318		status = "disabled";
319		#address-cells = <1>;
320		#size-cells = <0>;
321		clocks = <&clkctl1 MCUX_LCDIC_CLK>;
322		dmas = <&dma0 0>;
323	};
324
325	ctimer0: ctimer@28000 {
326		compatible = "nxp,lpc-ctimer";
327		reg = <0x28000 0x1000>;
328		interrupts = <10 0>;
329		status = "disabled";
330		clk-source = <1>;
331		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
332		mode = <0>;
333		input = <0>;
334		prescale = <0>;
335	};
336
337	ctimer1: ctimer@29000 {
338		compatible = "nxp,lpc-ctimer";
339		reg = <0x29000 0x1000>;
340		interrupts = <11 0>;
341		status = "disabled";
342		clk-source = <1>;
343		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
344		mode = <0>;
345		input = <0>;
346		prescale = <0>;
347	};
348
349	ctimer2: ctimer@2a000 {
350		compatible = "nxp,lpc-ctimer";
351		reg = <0x2a000 0x1000>;
352		interrupts = <39 0>;
353		status = "disabled";
354		clk-source = <1>;
355		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
356		mode = <0>;
357		input = <0>;
358		prescale = <0>;
359	};
360
361	ctimer3: ctimer@2b000 {
362		compatible = "nxp,lpc-ctimer";
363		reg = <0x2b000 0x1000>;
364		interrupts = <13 0>;
365		status = "disabled";
366		clk-source = <1>;
367		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
368		mode = <0>;
369		input = <0>;
370		prescale = <0>;
371	};
372
373	sctimer: pwm@146000 {
374		compatible = "nxp,sctimer-pwm";
375		reg = <0x146000 0x1000>;
376		interrupts = <12 0>;
377		clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
378		status = "disabled";
379		prescaler = <8>;
380		#pwm-cells = <3>;
381	};
382
383	mrt0: mrt@2d000 {
384		compatible = "nxp,mrt";
385		reg = <0x2d000 0x100>;
386		interrupts = <9 0>;
387		num-channels = <4>;
388		num-bits = <24>;
389		clocks = <&clkctl1 MCUX_MRT_CLK>;
390		resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
391		#address-cells = <1>;
392		#size-cells = <0>;
393
394		mrt0_channel0: mrt0_channel@0 {
395			compatible = "nxp,mrt-channel";
396			reg = <0>;
397			status = "disabled";
398		};
399		mrt0_channel1: mrt0_channel@1 {
400			compatible = "nxp,mrt-channel";
401			reg = <1>;
402			status = "disabled";
403		};
404		mrt0_channel2: mrt0_channel@2 {
405			compatible = "nxp,mrt-channel";
406			reg = <2>;
407			status = "disabled";
408		};
409		mrt0_channel3: mrt0_channel@3 {
410			compatible = "nxp,mrt-channel";
411			reg = <3>;
412			status = "disabled";
413		};
414	};
415
416	mrt1: mrt@3f000 {
417		compatible = "nxp,mrt";
418		reg = <0x3f000 0x100>;
419		interrupts = <23 0>;
420		num-channels = <4>;
421		num-bits = <24>;
422		clocks = <&clkctl1 MCUX_FREEMRT_CLK>;
423		resets = <&rstctl0 NXP_SYSCON_RESET(2, 26)>;
424		#address-cells = <1>;
425		#size-cells = <0>;
426
427		mrt1_channel0: mrt1_channel@0 {
428			compatible = "nxp,mrt-channel";
429			reg = <0>;
430			status = "disabled";
431		};
432		mrt1_channel1: mrt1_channel@1 {
433			compatible = "nxp,mrt-channel";
434			reg = <1>;
435			status = "disabled";
436		};
437		mrt1_channel2: mrt1_channel@2 {
438			compatible = "nxp,mrt-channel";
439			reg = <2>;
440			status = "disabled";
441		};
442		mrt1_channel3: mrt1_channel@3 {
443			compatible = "nxp,mrt-channel";
444			reg = <3>;
445			status = "disabled";
446		};
447	};
448
449	dmic0: dmic@121000 {
450		#address-cells=<1>;
451		#size-cells=<0>;
452		compatible = "nxp,dmic";
453		reg = <0x121000 0x1000>;
454		interrupts = <25 0>;
455		status = "disabled";
456		clocks = <&clkctl1 MCUX_DMIC_CLK>;
457
458		pdmc0: dmic-channel@0 {
459			reg = <0>;
460			dmas = <&dma0 16>;
461			status = "disabled";
462		};
463
464		pdmc1: dmic-channel@1 {
465			reg = <1>;
466			dmas = <&dma0 17>;
467			status = "disabled";
468		};
469
470		pdmc2: dmic-channel@2 {
471			reg = <2>;
472			dmas = <&dma0 18>;
473			status = "disabled";
474		};
475
476		pdmc3: dmic-channel@3 {
477			reg = <3>;
478			dmas = <&dma0 19>;
479			status = "disabled";
480		};
481	};
482
483	gau {
484		ranges = <>;
485		#address-cells = <1>;
486		#size-cells = <1>;
487
488		adc0: gau_adc0@38000 {
489			compatible = "nxp,gau-adc";
490			reg = <0x38000 0x100>;
491			interrupts = <112 0>;
492			status = "disabled";
493			#io-channel-cells = <1>;
494		};
495
496		adc1: gau_adc1@38100 {
497			compatible = "nxp,gau-adc";
498			reg = <0x38100 0x100>;
499			interrupts = <111 0>;
500			status = "disabled";
501			#io-channel-cells = <1>;
502		};
503
504		dac0: dac@38200 {
505			compatible = "nxp,gau-dac";
506			reg = <0x38200 0x30>;
507			interrupts = <108 0>;
508			status = "disabled";
509			#io-channel-cells = <0>;
510		};
511	};
512
513	os_timer: timers@13b000 {
514		compatible = "nxp,os-timer";
515		reg = <0x13b000 0x1000>;
516		interrupts = <41 0>;
517		status = "disabled";
518	};
519
520	nbu: nbu {
521		compatible = "nxp,nbu";
522		interrupts = <90 2>, <82 2>;
523		interrupt-names = "nbu_rx_int", "wakeup_int";
524	};
525
526	hci: hci_ble {
527		compatible = "nxp,hci-ble";
528	};
529
530	hdlc_rcp_if: hdlc_rcp_if {
531		compatible = "nxp,hdlc-rcp-if";
532		interrupts = <90 2>, <82 2>;
533		interrupt-names = "hdlc_rcp_if_int", "wakeup_int";
534	};
535
536	enet: enet@138000 {
537		compatible = "nxp,enet";
538		reg = <0x138000 0x700>;
539		clocks = <&clkctl1 MCUX_ENET_CLK>;
540		enet_mac: ethernet {
541			compatible = "nxp,enet-mac";
542			interrupts = <115 0>;
543			interrupt-names = "COMMON";
544			nxp,mdio = <&enet_mdio>;
545			nxp,ptp-clock = <&enet_ptp_clock>;
546			status = "disabled";
547		};
548		enet_mdio: mdio {
549			compatible = "nxp,enet-mdio";
550			status = "disabled";
551			#address-cells = <1>;
552			#size-cells = <0>;
553		};
554		enet_ptp_clock: ptp-clock {
555			compatible = "nxp,enet-ptp-clock";
556			interrupts = <116 0>;
557			status = "disabled";
558			clocks = <&clkctl1 MCUX_ENET_PLL>;
559		};
560	};
561};
562
563&flexspi {
564	compatible = "nxp,imx-flexspi";
565	status = "disabled";
566	interrupts = <42 0>;
567	#address-cells = <1>;
568	#size-cells = <0>;
569	clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
570};
571
572&nvic {
573	arm,num-irq-priority-bits = <3>;
574};
575