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/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_efuse_v3.c136 cy_en_efuse_status_t Cy_EFUSE_WriteBit(EFUSE_Type *base, uint32_t bitPos, uint32_t offset) in Cy_EFUSE_WriteBit()
199 cy_en_efuse_status_t Cy_EFUSE_WriteByte(EFUSE_Type *base, uint32_t src, uint32_t offset) in Cy_EFUSE_WriteByte()
234 cy_en_efuse_status_t Cy_EFUSE_WriteWord(EFUSE_Type *base, uint32_t src, uint32_t offset) in Cy_EFUSE_WriteWord()
268 cy_en_efuse_status_t Cy_EFUSE_WriteWordArray(EFUSE_Type *base, const uint32_t *src, uint32_t offset… in Cy_EFUSE_WriteWordArray()
300 …n_efuse_status_t Cy_EFUSE_ReadBit(EFUSE_Type *base, uint8_t *dst, uint32_t bitPos, uint32_t offset) in Cy_EFUSE_ReadBit()
325 cy_en_efuse_status_t Cy_EFUSE_ReadByte(EFUSE_Type *base, uint8_t *dst, uint32_t offset) in Cy_EFUSE_ReadByte()
356 cy_en_efuse_status_t Cy_EFUSE_ReadWord(EFUSE_Type *base, uint32_t *dst, uint32_t offset) in Cy_EFUSE_ReadWord()
377 cy_en_efuse_status_t Cy_EFUSE_ReadWordArray(EFUSE_Type *base, uint32_t *dst, uint32_t offset, uint3… in Cy_EFUSE_ReadWordArray()
Dcy_efuse.c61 uint32_t offset = bitNum / CY_EFUSE_BITS_PER_BYTE; in Cy_EFUSE_GetEfuseBit() local
78 cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal) in Cy_EFUSE_GetEfuseByte()
Dcy_cryptolite_hkdf.c151 uint32_t offset=0u; in Cy_Cryptolite_Hkdf_Expand() local
Dcy_crypto_core_hkdf_v2.c204 uint32_t offset=0u; in Cy_Crypto_Core_V2_Hkdf_Expand() local
Dcy_adcmic.c394 void Cy_ADCMic_SetDcOffset(int16_t offset, cy_stc_adcmic_context_t * context) in Cy_ADCMic_SetDcOffset()
Dcy_smif_hb_flash.c703 …us_EraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t *memConfig, uint32_t offset, cy_stc_smif_… in Cy_SMIF_HyperBus_EraseSector()
Dcy_sar.c1043 cy_en_sar_status_t Cy_SAR_SetChannelOffset(const SAR_Type *base, uint32_t chan, int16_t offset) in Cy_SAR_SetChannelOffset()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_csd.h725 __STATIC_INLINE uint32_t Cy_CSD_ReadReg(const CSD_Type * base, uint32_t offset) in Cy_CSD_ReadReg()
747 __STATIC_INLINE void Cy_CSD_WriteReg(CSD_Type * base, uint32_t offset, uint32_t value) in Cy_CSD_WriteReg()
770 __STATIC_INLINE void Cy_CSD_SetBits(CSD_Type * base, uint32_t offset, uint32_t mask) in Cy_CSD_SetBits()
794 __STATIC_INLINE void Cy_CSD_ClrBits(CSD_Type * base, uint32_t offset, uint32_t mask) in Cy_CSD_ClrBits()
821 __STATIC_INLINE void Cy_CSD_WriteBits(CSD_Type * base, uint32_t offset, uint32_t mask, uint32_t val… in Cy_CSD_WriteBits()
Dcy_crypto_core_hw_v2.h309 __STATIC_INLINE void Cy_Crypto_Core_V2_RBXor(CRYPTO_Type *base, uint32_t offset, uint32_t size) in Cy_Crypto_Core_V2_RBXor()
321 __STATIC_INLINE void Cy_Crypto_Core_V2_RBStore(CRYPTO_Type *base, uint32_t offset, uint32_t size) in Cy_Crypto_Core_V2_RBStore()
332 __STATIC_INLINE void Cy_Crypto_Core_V2_RBSetByte(CRYPTO_Type *base, uint32_t offset, uint8_t byte) in Cy_Crypto_Core_V2_RBSetByte()
Dcy_sar2.h620 uint16_t offset; /**< Digital offset correction. The valid range is [0..4095] */ member
626 int8_t offset; /**< Analog offset correction. The valid range is [-128..127] */ member
/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/bus_protocols/
Dwhd_chip_reg.h34 #define D11REG_ADDR(offset) (D11_BASE_ADDR + offset) argument
35 #define D11IHR_ADDR(offset) (D11_AXI_BASE_ADDR + 0x400 + (2 * offset) ) argument
36 #define D11SHM_ADDR(offset) (D11_SHM_BASE_ADDR + offset) argument
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_irq_impl.c74 uint8_t offset = bit - start_bit; in _cyhal_system_irq_lookup_priority() local
89 uint8_t offset = bit - start_bit; in _cyhal_system_irq_store_priority() local
/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/resources/resource_imp/
Dwhd_resources.c95 resource_result_t resource_read(const resource_hnd_t *resource, uint32_t offset, uint32_t maxsize, … in resource_read()
319 uint32_t offset, uint32_t size, uint32_t *size_out, void *buffer) in host_resource_read()
Dwiced_resource.h135 unsigned long offset; /**< Offset to the start of the resource */ member
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_ccu4.c780 uint8_t offset; in XMC_CCU4_SLICE_ConfigureEvent() local
858 uint8_t offset; in XMC_CCU4_SLICE_SetInput() local
Dxmc_ccu8.c827 uint8_t offset; in XMC_CCU8_SLICE_ConfigureEvent() local
906 uint8_t offset; in XMC_CCU8_SLICE_SetInput() local
Dxmc1_scu.c819 int32_t offset; in XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature() local
/hal_infineon-latest/btstack/wiced_include/
Dwiced_bt_gatt.h252 uint16_t offset; /**< Offset to read */ member
293 …uint16_t offset; /**< Attribute value offset, ignored if no… member
302 uint16_t offset; /**< Offset to write */ member
360 uint16_t offset; /**< offset */ member
/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/
Dwhd_resource_if.c104 uint32_t whd_resource_read(whd_driver_t whd_driver, whd_resource_type_t type, uint32_t offset, in whd_resource_read()
Dwhd_chip_constants.c141 uint32_t offset = 0; in get_socsram_base_address() local
/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_nvm.h131 uint32_t offset; //!< Offset to the address in the distinct NVM region. member
/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_dsd.h416 …int16_t offset; /**< Offset subtracted from result.This parameter can take a value of int16_t */ member
918 …ATIC_INLINE void XMC_DSD_CH_MainFilter_SetOffset(XMC_DSD_CH_t *const channel, const int16_t offset) in XMC_DSD_CH_MainFilter_SetOffset()
Dxmc_dac.h1179 … void XMC_DAC_CH_SetOutputOffset(XMC_DAC_t *const dac, const uint8_t channel, const uint8_t offset) in XMC_DAC_CH_SetOutputOffset()
/hal_infineon-latest/btstack-integration/COMPONENT_BTSS-IPC/platform/common/
Dcybt_prm.c291 uint32_t len, offset = cybt_prm_cb.tx_patch_length; in cybt_prm_send_next_patch() local
/hal_infineon-latest/mtb-pdl-cat1/drivers/third_party/ethernet/src/
Dedd.c2785 uint32_t emacSetRxBufOffset(void *pD, uint8_t offset) in emacSetRxBufOffset()
2796 uint32_t emacGetRxBufOffset(void *pD, uint8_t *offset) in emacGetRxBufOffset()

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