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Searched defs:i2cx (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_i2c.h49 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control reg… argument
50 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control reg… argument
51 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave addre… argument
52 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave addre… argument
53 #define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer bu… argument
54 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer st… argument
55 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer st… argument
56 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock confi… argument
57 #define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time r… argument
58 #define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control… argument
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/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_i2c.h46 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0… argument
47 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1… argument
48 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address regi… argument
49 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address regi… argument
50 #define I2C_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */ argument
51 #define I2C_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */ argument
52 #define I2C_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */ argument
53 #define I2C_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear regis… argument
54 #define I2C_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */ argument
55 #define I2C_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data regis… argument
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/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_i2c.h45 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0… argument
46 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1… argument
47 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address regi… argument
48 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address regi… argument
49 #define I2C_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */ argument
50 #define I2C_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */ argument
51 #define I2C_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */ argument
52 #define I2C_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear regis… argument
53 #define I2C_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */ argument
54 #define I2C_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data regis… argument
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/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_i2c.h49 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 … argument
50 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 … argument
51 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address regis… argument
52 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address regis… argument
53 #define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer reg… argument
54 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status reg… argument
55 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status reg… argument
56 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure reg… argument
57 #define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register … argument
58 #define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and sta… argument
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/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_i2c.h46 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ argument
47 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ argument
48 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ argument
49 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ argument
50 #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register … argument
51 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register … argument
52 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register … argument
53 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register … argument
54 #define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ argument
55 #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure … argument
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/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_i2c.h47 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 … argument
48 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 … argument
49 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address regis… argument
50 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address regis… argument
51 #define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer reg… argument
52 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status reg… argument
53 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status reg… argument
54 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure reg… argument
55 #define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register … argument
56 #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast-mode-plus conf… argument
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_i2c.h48 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ argument
49 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ argument
50 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ argument
51 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ argument
52 #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register … argument
53 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register … argument
54 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register … argument
55 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register … argument
56 #define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ argument
57 #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure … argument
[all …]
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_i2c.h50 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0… argument
51 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1… argument
52 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address regi… argument
53 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address regi… argument
54 #define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer re… argument
55 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status re… argument
56 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status re… argument
57 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure re… argument
58 #define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register… argument
59 #define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control reg… argument
[all …]