1 /*
2 * Copyright (c) 2021 NXP Semiconductor INC.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /** @file
9 * @brief I2S bus (SAI) driver for NXP i.MX RT series.
10 */
11
12 #include <errno.h>
13 #include <string.h>
14 #include <zephyr/sys/__assert.h>
15 #include <zephyr/kernel.h>
16 #include <zephyr/device.h>
17 #include <zephyr/init.h>
18 #include <zephyr/drivers/dma.h>
19 #include <zephyr/drivers/i2s.h>
20 #include <zephyr/drivers/pinctrl.h>
21 #include <zephyr/drivers/clock_control.h>
22 #include <zephyr/dt-bindings/clock/imx_ccm.h>
23 #include <zephyr/sys/barrier.h>
24 #include <soc.h>
25
26 #include "i2s_mcux_sai.h"
27
28 #define LOG_DOMAIN dev_i2s_mcux
29 #define LOG_LEVEL CONFIG_I2S_LOG_LEVEL
30 #include <zephyr/logging/log.h>
31 #include <zephyr/irq.h>
32
33 LOG_MODULE_REGISTER(LOG_DOMAIN);
34
35 #define DT_DRV_COMPAT nxp_mcux_i2s
36 #define NUM_DMA_BLOCKS_RX_PREP 3
37 #define MAX_TX_DMA_BLOCKS CONFIG_DMA_TCD_QUEUE_SIZE
38 #if (NUM_DMA_BLOCKS_RX_PREP >= CONFIG_DMA_TCD_QUEUE_SIZE)
39 #error NUM_DMA_BLOCKS_RX_PREP must be < CONFIG_DMA_TCD_QUEUE_SIZE
40 #endif
41 #if defined(CONFIG_DMA_MCUX_EDMA) && (NUM_DMA_BLOCKS_RX_PREP < 3)
42 #error eDMA avoids TCD coherency issue if NUM_DMA_BLOCKS_RX_PREP >= 3
43 #endif
44
45 /*
46 * SAI driver uses source_gather_en/dest_scatter_en feature of DMA, and relies
47 * on DMA driver managing circular list of DMA blocks. Like eDMA driver links
48 * Transfer Control Descriptors (TCDs) in list, and manages the tcdpool.
49 * Calling dma_reload() adds new DMA block to DMA channel already configured,
50 * into the DMA driver's circular list of blocks.
51
52 * This indicates the Tx/Rx stream.
53 *
54 * in_queue and out_queue are used as follows
55 * transmit stream:
56 * application provided buffer is queued to in_queue until loaded to DMA.
57 * when DMA channel is idle, buffer is retrieved from in_queue and loaded
58 * to DMA and queued to out_queue. when DMA completes, buffer is retrieved
59 * from out_queue and freed.
60 *
61 * receive stream:
62 * driver allocates buffer from slab and loads DMA buffer is queued to
63 * in_queue when DMA completes, buffer is retrieved from in_queue
64 * and queued to out_queue when application reads, buffer is read
65 * (may optionally block) from out_queue and presented to application.
66 */
67 struct stream {
68 int32_t state;
69 uint32_t dma_channel;
70 uint32_t start_channel;
71 void (*irq_call_back)(void);
72 struct i2s_config cfg;
73 struct dma_config dma_cfg;
74 struct dma_block_config dma_block;
75 uint8_t free_tx_dma_blocks;
76 bool last_block;
77 struct k_msgq in_queue;
78 struct k_msgq out_queue;
79 };
80
81 struct i2s_mcux_config {
82 I2S_Type *base;
83 uint32_t clk_src;
84 uint32_t clk_pre_div;
85 uint32_t clk_src_div;
86 uint32_t pll_src;
87 uint32_t pll_lp;
88 uint32_t pll_pd;
89 uint32_t pll_num;
90 uint32_t pll_den;
91 uint32_t mclk_pin_mask;
92 uint32_t mclk_pin_offset;
93 uint32_t tx_channel;
94 clock_control_subsys_t clk_sub_sys;
95 const struct device *ccm_dev;
96 const struct pinctrl_dev_config *pinctrl;
97 void (*irq_connect)(const struct device *dev);
98 bool rx_sync_mode;
99 bool tx_sync_mode;
100 };
101
102 /* Device run time data */
103 struct i2s_dev_data {
104 const struct device *dev_dma;
105 struct stream tx;
106 void *tx_in_msgs[CONFIG_I2S_TX_BLOCK_COUNT];
107 void *tx_out_msgs[CONFIG_I2S_TX_BLOCK_COUNT];
108 struct stream rx;
109 void *rx_in_msgs[CONFIG_I2S_RX_BLOCK_COUNT];
110 void *rx_out_msgs[CONFIG_I2S_RX_BLOCK_COUNT];
111 };
112
113 static void i2s_dma_tx_callback(const struct device *, void *,
114 uint32_t, int);
115 static void i2s_tx_stream_disable(const struct device *, bool drop);
116 static void i2s_rx_stream_disable(const struct device *,
117 bool in_drop, bool out_drop);
118
i2s_purge_stream_buffers(struct stream * strm,struct k_mem_slab * mem_slab,bool in_drop,bool out_drop)119 static inline void i2s_purge_stream_buffers(struct stream *strm,
120 struct k_mem_slab *mem_slab,
121 bool in_drop, bool out_drop)
122 {
123 void *buffer;
124
125 if (in_drop) {
126 while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) {
127 k_mem_slab_free(mem_slab, buffer);
128 }
129 }
130
131 if (out_drop) {
132 while (k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT) == 0) {
133 k_mem_slab_free(mem_slab, buffer);
134 }
135 }
136 }
137
i2s_tx_stream_disable(const struct device * dev,bool drop)138 static void i2s_tx_stream_disable(const struct device *dev, bool drop)
139 {
140 struct i2s_dev_data *dev_data = dev->data;
141 struct stream *strm = &dev_data->tx;
142 const struct device *dev_dma = dev_data->dev_dma;
143 const struct i2s_mcux_config *dev_cfg = dev->config;
144
145 LOG_DBG("Stopping DMA channel %u for TX stream", strm->dma_channel);
146
147 /* Disable FIFO DMA request */
148 SAI_TxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable,
149 false);
150
151 dma_stop(dev_dma, strm->dma_channel);
152
153 /* wait for TX FIFO to drain before disabling */
154 while ((dev_cfg->base->TCSR & I2S_TCSR_FWF_MASK) == 0)
155 ;
156
157 /* Disable the channel FIFO */
158 dev_cfg->base->TCR3 &= ~I2S_TCR3_TCE_MASK;
159
160 /* Disable Tx */
161 SAI_TxEnable(dev_cfg->base, false);
162
163 /* If Tx is disabled, reset the FIFO pointer, clear error flags */
164 if ((dev_cfg->base->TCSR & I2S_TCSR_TE_MASK) == 0UL) {
165 dev_cfg->base->TCSR |=
166 (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK);
167 dev_cfg->base->TCSR &= ~I2S_TCSR_SR_MASK;
168 }
169
170 /* purge buffers queued in the stream */
171 if (drop) {
172 i2s_purge_stream_buffers(strm, dev_data->tx.cfg.mem_slab,
173 true, true);
174 }
175 }
176
i2s_rx_stream_disable(const struct device * dev,bool in_drop,bool out_drop)177 static void i2s_rx_stream_disable(const struct device *dev,
178 bool in_drop, bool out_drop)
179 {
180 struct i2s_dev_data *dev_data = dev->data;
181 struct stream *strm = &dev_data->rx;
182 const struct device *dev_dma = dev_data->dev_dma;
183 const struct i2s_mcux_config *dev_cfg = dev->config;
184
185 LOG_DBG("Stopping RX stream & DMA channel %u", strm->dma_channel);
186 dma_stop(dev_dma, strm->dma_channel);
187
188 /* Disable the channel FIFO */
189 dev_cfg->base->RCR3 &= ~I2S_RCR3_RCE_MASK;
190
191 /* Disable DMA enable bit */
192 SAI_RxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable,
193 false);
194
195 /* Disable Rx */
196 SAI_RxEnable(dev_cfg->base, false);
197
198 /* wait for Receiver to disable */
199 while (dev_cfg->base->RCSR & I2S_RCSR_RE_MASK)
200 ;
201 /* reset the FIFO pointer and clear error flags */
202 dev_cfg->base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK);
203 dev_cfg->base->RCSR &= ~I2S_RCSR_SR_MASK;
204
205 /* purge buffers queued in the stream */
206 if (in_drop || out_drop) {
207 i2s_purge_stream_buffers(strm, dev_data->rx.cfg.mem_slab,
208 in_drop, out_drop);
209 }
210 }
211
i2s_tx_reload_multiple_dma_blocks(const struct device * dev,uint8_t * blocks_queued)212 static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev,
213 uint8_t *blocks_queued)
214 {
215 struct i2s_dev_data *dev_data = dev->data;
216 const struct i2s_mcux_config *dev_cfg = dev->config;
217 I2S_Type *base = (I2S_Type *)dev_cfg->base;
218 struct stream *strm = &dev_data->tx;
219 void *buffer = NULL;
220 int ret = 0;
221 unsigned int key;
222
223 *blocks_queued = 0;
224
225 key = irq_lock();
226
227 /* queue additional blocks to DMA if in_queue and DMA has free blocks */
228 while (strm->free_tx_dma_blocks) {
229 /* get the next buffer from queue */
230 ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
231 if (ret) {
232 /* in_queue is empty, no more blocks to send to DMA */
233 ret = 0;
234 break;
235 }
236
237 /* reload the DMA */
238 ret = dma_reload(dev_data->dev_dma, strm->dma_channel,
239 (uint32_t)buffer,
240 (uint32_t)&base->TDR[strm->start_channel],
241 strm->cfg.block_size);
242 if (ret != 0) {
243 LOG_ERR("dma_reload() failed with error 0x%x", ret);
244 break;
245 }
246
247 (strm->free_tx_dma_blocks)--;
248
249 ret = k_msgq_put(&strm->out_queue,
250 &buffer, K_NO_WAIT);
251 if (ret != 0) {
252 LOG_ERR("buffer %p -> out %p err %d",
253 buffer, &strm->out_queue, ret);
254 break;
255 }
256
257 (*blocks_queued)++;
258 }
259
260 irq_unlock(key);
261 return ret;
262 }
263
264 /* This function is executed in the interrupt context */
i2s_dma_tx_callback(const struct device * dma_dev,void * arg,uint32_t channel,int status)265 static void i2s_dma_tx_callback(const struct device *dma_dev,
266 void *arg, uint32_t channel, int status)
267 {
268 const struct device *dev = (struct device *)arg;
269 struct i2s_dev_data *dev_data = dev->data;
270 struct stream *strm = &dev_data->tx;
271 void *buffer = NULL;
272 int ret;
273 uint8_t blocks_queued;
274
275 LOG_DBG("tx cb");
276
277 ret = k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT);
278 if (ret == 0) {
279 /* transmission complete. free the buffer */
280 k_mem_slab_free(strm->cfg.mem_slab, buffer);
281 (strm->free_tx_dma_blocks)++;
282 } else {
283 LOG_ERR("no buf in out_queue for channel %u", channel);
284 }
285
286 if (strm->free_tx_dma_blocks > MAX_TX_DMA_BLOCKS) {
287 strm->state = I2S_STATE_ERROR;
288 LOG_ERR("free_tx_dma_blocks exceeded maximum, now %d",
289 strm->free_tx_dma_blocks);
290 goto disabled_exit_no_drop;
291 }
292
293 /* Received a STOP trigger, terminate TX immediately */
294 if (strm->last_block) {
295 strm->state = I2S_STATE_READY;
296 LOG_DBG("TX STOPPED last_block set");
297 goto disabled_exit_no_drop;
298 }
299
300 if (ret) {
301 /* k_msgq_get() returned error, and was not last_block */
302 strm->state = I2S_STATE_ERROR;
303 goto disabled_exit_no_drop;
304 }
305
306 switch (strm->state) {
307 case I2S_STATE_RUNNING:
308 case I2S_STATE_STOPPING:
309 ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
310
311 if (ret) {
312 strm->state = I2S_STATE_ERROR;
313 goto disabled_exit_no_drop;
314 }
315 dma_start(dev_data->dev_dma, strm->dma_channel);
316
317 if (blocks_queued ||
318 (strm->free_tx_dma_blocks < MAX_TX_DMA_BLOCKS)) {
319 goto enabled_exit;
320 } else {
321 /* all DMA blocks are free but no blocks were queued */
322 if (strm->state == I2S_STATE_STOPPING) {
323 /* TX queue has drained */
324 strm->state = I2S_STATE_READY;
325 LOG_DBG("TX stream has stopped");
326 } else {
327 strm->state = I2S_STATE_ERROR;
328 LOG_ERR("TX Failed to reload DMA");
329 }
330 goto disabled_exit_no_drop;
331 }
332
333 case I2S_STATE_ERROR:
334 default:
335 goto disabled_exit_drop;
336 }
337
338 disabled_exit_no_drop:
339 i2s_tx_stream_disable(dev, false);
340 return;
341
342 disabled_exit_drop:
343 i2s_tx_stream_disable(dev, true);
344 return;
345
346 enabled_exit:
347 return;
348 }
349
i2s_dma_rx_callback(const struct device * dma_dev,void * arg,uint32_t channel,int status)350 static void i2s_dma_rx_callback(const struct device *dma_dev,
351 void *arg, uint32_t channel, int status)
352 {
353 struct device *dev = (struct device *)arg;
354 const struct i2s_mcux_config *dev_cfg = dev->config;
355 I2S_Type *base = (I2S_Type *)dev_cfg->base;
356 struct i2s_dev_data *dev_data = dev->data;
357 struct stream *strm = &dev_data->rx;
358 void *buffer;
359 int ret;
360
361 LOG_DBG("RX cb");
362
363 switch (strm->state) {
364 case I2S_STATE_STOPPING:
365 case I2S_STATE_RUNNING:
366 /* retrieve buffer from input queue */
367 ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
368 __ASSERT_NO_MSG(ret == 0);
369
370 /* put buffer to output queue */
371 ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
372 if (ret != 0) {
373 LOG_ERR("buffer %p -> out_queue %p err %d",
374 buffer,
375 &strm->out_queue, ret);
376 i2s_rx_stream_disable(dev, false, false);
377 strm->state = I2S_STATE_ERROR;
378 return;
379 }
380 if (strm->state == I2S_STATE_RUNNING) {
381 /* allocate new buffer for next audio frame */
382 ret = k_mem_slab_alloc(strm->cfg.mem_slab,
383 &buffer, K_NO_WAIT);
384 if (ret != 0) {
385 LOG_ERR("buffer alloc from slab %p err %d",
386 strm->cfg.mem_slab, ret);
387 i2s_rx_stream_disable(dev, false, false);
388 strm->state = I2S_STATE_ERROR;
389 } else {
390 uint32_t data_path = strm->start_channel;
391
392 ret = dma_reload(dev_data->dev_dma,
393 strm->dma_channel,
394 (uint32_t)&base->RDR[data_path],
395 (uint32_t)buffer,
396 strm->cfg.block_size);
397 if (ret != 0) {
398 LOG_ERR("dma_reload() failed with error 0x%x",
399 ret);
400 i2s_rx_stream_disable(dev,
401 false, false);
402 strm->state = I2S_STATE_ERROR;
403 return;
404 }
405
406 /* put buffer in input queue */
407 ret = k_msgq_put(&strm->in_queue,
408 &buffer, K_NO_WAIT);
409 if (ret != 0) {
410 LOG_ERR("%p -> in_queue %p err %d",
411 buffer, &strm->in_queue,
412 ret);
413 }
414
415 dma_start(dev_data->dev_dma,
416 strm->dma_channel);
417 }
418 } else {
419 i2s_rx_stream_disable(dev, true, false);
420 /* Received a STOP/DRAIN trigger */
421 strm->state = I2S_STATE_READY;
422 }
423 break;
424 case I2S_STATE_ERROR:
425 i2s_rx_stream_disable(dev, true, true);
426 break;
427 }
428 }
429
enable_mclk_direction(const struct device * dev,bool dir)430 static void enable_mclk_direction(const struct device *dev, bool dir)
431 {
432 const struct i2s_mcux_config *dev_cfg = dev->config;
433 uint32_t offset = dev_cfg->mclk_pin_offset;
434 uint32_t mask = dev_cfg->mclk_pin_mask;
435 uint32_t *gpr = (uint32_t *)
436 (DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset);
437
438 if (dir) {
439 *gpr |= mask;
440 } else {
441 *gpr &= ~mask;
442 }
443
444 }
445
get_mclk_rate(const struct device * dev,uint32_t * mclk)446 static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
447 {
448 const struct i2s_mcux_config *dev_cfg = dev->config;
449 const struct device *ccm_dev = dev_cfg->ccm_dev;
450 clock_control_subsys_t clk_sub_sys = dev_cfg->clk_sub_sys;
451 uint32_t rate = 0;
452
453 if (device_is_ready(ccm_dev)) {
454 clock_control_get_rate(ccm_dev, clk_sub_sys, &rate);
455 } else {
456 LOG_ERR("CCM driver is not installed");
457 *mclk = rate;
458 return;
459 }
460 *mclk = rate;
461 }
462
i2s_mcux_config(const struct device * dev,enum i2s_dir dir,const struct i2s_config * i2s_cfg)463 static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
464 const struct i2s_config *i2s_cfg)
465 {
466 const struct i2s_mcux_config *dev_cfg = dev->config;
467 I2S_Type *base = (I2S_Type *)dev_cfg->base;
468 struct i2s_dev_data *dev_data = dev->data;
469 sai_transceiver_t config;
470 uint32_t mclk;
471 /*num_words is frame size*/
472 uint8_t num_words = i2s_cfg->channels;
473 uint8_t word_size_bits = i2s_cfg->word_size;
474
475 if ((dev_data->tx.state != I2S_STATE_NOT_READY) &&
476 (dev_data->tx.state != I2S_STATE_READY) &&
477 (dev_data->rx.state != I2S_STATE_NOT_READY) &&
478 (dev_data->rx.state != I2S_STATE_READY)) {
479 LOG_ERR("invalid state tx(%u) rx(%u)",
480 dev_data->tx.state,
481 dev_data->rx.state);
482 if (dir == I2S_DIR_TX) {
483 dev_data->tx.state = I2S_STATE_NOT_READY;
484 } else {
485 dev_data->rx.state = I2S_STATE_NOT_READY;
486 }
487 return -EINVAL;
488 }
489
490 if (i2s_cfg->frame_clk_freq == 0U) {
491 LOG_ERR("Invalid frame_clk_freq %u",
492 i2s_cfg->frame_clk_freq);
493 if (dir == I2S_DIR_TX) {
494 dev_data->tx.state = I2S_STATE_NOT_READY;
495 } else {
496 dev_data->rx.state = I2S_STATE_NOT_READY;
497 }
498 return 0;
499 }
500
501 if (word_size_bits < SAI_WORD_SIZE_BITS_MIN ||
502 word_size_bits > SAI_WORD_SIZE_BITS_MAX) {
503 LOG_ERR("Unsupported I2S word size %u", word_size_bits);
504 if (dir == I2S_DIR_TX) {
505 dev_data->tx.state = I2S_STATE_NOT_READY;
506 } else {
507 dev_data->rx.state = I2S_STATE_NOT_READY;
508 }
509 return -EINVAL;
510 }
511
512 if (num_words < SAI_WORD_PER_FRAME_MIN ||
513 num_words > SAI_WORD_PER_FRAME_MAX) {
514 LOG_ERR("Unsupported words length %u", num_words);
515 if (dir == I2S_DIR_TX) {
516 dev_data->tx.state = I2S_STATE_NOT_READY;
517 } else {
518 dev_data->rx.state = I2S_STATE_NOT_READY;
519 }
520 return -EINVAL;
521 }
522
523 if ((i2s_cfg->options & I2S_OPT_PINGPONG) == I2S_OPT_PINGPONG) {
524 LOG_ERR("Ping-pong mode not supported");
525 if (dir == I2S_DIR_TX) {
526 dev_data->tx.state = I2S_STATE_NOT_READY;
527 } else {
528 dev_data->rx.state = I2S_STATE_NOT_READY;
529 }
530 return -ENOTSUP;
531 }
532
533 memset(&config, 0, sizeof(config));
534
535 const bool is_mclk_slave = i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE;
536
537 enable_mclk_direction(dev, !is_mclk_slave);
538
539 get_mclk_rate(dev, &mclk);
540 LOG_DBG("mclk is %d", mclk);
541
542 /* bit clock source is MCLK */
543 config.bitClock.bclkSource = kSAI_BclkSourceMclkDiv;
544 /*
545 * additional settings for bclk
546 * read the SDK header file for more details
547 */
548 config.bitClock.bclkInputDelay = false;
549
550 /* frame sync default configurations */
551 #if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && \
552 FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
553 config.frameSync.frameSyncGenerateOnDemand = false;
554 #endif
555
556 /* serial data default configurations */
557 #if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && \
558 FSL_FEATURE_SAI_HAS_CHANNEL_MODE
559 config.serialData.dataMode = kSAI_DataPinStateOutputZero;
560 #endif
561
562 config.frameSync.frameSyncPolarity = kSAI_PolarityActiveLow;
563 config.bitClock.bclkSrcSwap = false;
564 /* format */
565 switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
566 case I2S_FMT_DATA_FORMAT_I2S:
567 SAI_GetClassicI2SConfig(&config, word_size_bits,
568 kSAI_Stereo,
569 dev_cfg->tx_channel);
570 break;
571 case I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED:
572 SAI_GetLeftJustifiedConfig(&config, word_size_bits,
573 kSAI_Stereo,
574 dev_cfg->tx_channel);
575 break;
576 case I2S_FMT_DATA_FORMAT_PCM_SHORT:
577 SAI_GetDSPConfig(&config, kSAI_FrameSyncLenOneBitClk,
578 word_size_bits, kSAI_Stereo,
579 dev_cfg->tx_channel);
580 /* We need to set the data word count manually, since the HAL
581 * function does not
582 */
583 config.serialData.dataWordNum = num_words;
584 config.frameSync.frameSyncEarly = true;
585 config.bitClock.bclkPolarity = kSAI_SampleOnFallingEdge;
586 break;
587 case I2S_FMT_DATA_FORMAT_PCM_LONG:
588 SAI_GetTDMConfig(&config, kSAI_FrameSyncLenPerWordWidth,
589 word_size_bits, num_words,
590 dev_cfg->tx_channel);
591 config.bitClock.bclkPolarity = kSAI_SampleOnFallingEdge;
592 break;
593 default:
594 LOG_ERR("Unsupported I2S data format");
595 if (dir == I2S_DIR_TX) {
596 dev_data->tx.state = I2S_STATE_NOT_READY;
597 } else {
598 dev_data->rx.state = I2S_STATE_NOT_READY;
599 }
600 return -EINVAL;
601 }
602
603 /* sync mode configurations */
604 if (dir == I2S_DIR_TX) {
605 /* TX */
606 if (dev_cfg->tx_sync_mode) {
607 config.syncMode = kSAI_ModeSync;
608 } else {
609 config.syncMode = kSAI_ModeAsync;
610 }
611 } else {
612 /* RX */
613 if (dev_cfg->rx_sync_mode) {
614 config.syncMode = kSAI_ModeSync;
615 } else {
616 config.syncMode = kSAI_ModeAsync;
617 }
618 }
619
620 if (i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) {
621 if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) {
622 config.masterSlave = kSAI_Slave;
623 } else {
624 config.masterSlave =
625 kSAI_Bclk_Master_FrameSync_Slave;
626 }
627 } else {
628 if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) {
629 config.masterSlave =
630 kSAI_Bclk_Slave_FrameSync_Master;
631 } else {
632 config.masterSlave = kSAI_Master;
633 }
634 }
635
636 /* clock signal polarity */
637 switch (i2s_cfg->format & I2S_FMT_CLK_FORMAT_MASK) {
638 case I2S_FMT_CLK_NF_NB:
639 /* No action required, leave the configuration untouched */
640 break;
641
642 case I2S_FMT_CLK_NF_IB:
643 /* Swap bclk polarity */
644 config.bitClock.bclkPolarity =
645 (config.bitClock.bclkPolarity == kSAI_SampleOnFallingEdge) ?
646 kSAI_SampleOnRisingEdge :
647 kSAI_SampleOnFallingEdge;
648 break;
649
650 case I2S_FMT_CLK_IF_NB:
651 /* Swap frame sync polarity */
652 config.frameSync.frameSyncPolarity =
653 (config.frameSync.frameSyncPolarity == kSAI_PolarityActiveHigh) ?
654 kSAI_PolarityActiveLow :
655 kSAI_PolarityActiveHigh;
656 break;
657
658 case I2S_FMT_CLK_IF_IB:
659 /* Swap frame sync and bclk polarity */
660 config.frameSync.frameSyncPolarity =
661 (config.frameSync.frameSyncPolarity == kSAI_PolarityActiveHigh) ?
662 kSAI_PolarityActiveLow :
663 kSAI_PolarityActiveHigh;
664 config.bitClock.bclkPolarity =
665 (config.bitClock.bclkPolarity == kSAI_SampleOnFallingEdge) ?
666 kSAI_SampleOnRisingEdge :
667 kSAI_SampleOnFallingEdge;
668 break;
669 }
670
671 /* PCM short format always requires that WS be one BCLK cycle */
672 if ((i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) !=
673 I2S_FMT_DATA_FORMAT_PCM_SHORT) {
674 config.frameSync.frameSyncWidth = (uint8_t)word_size_bits;
675 }
676
677 if (dir == I2S_DIR_TX) {
678 memcpy(&dev_data->tx.cfg, i2s_cfg, sizeof(struct i2s_config));
679 LOG_DBG("tx slab free_list = 0x%x",
680 (uint32_t)i2s_cfg->mem_slab->free_list);
681 LOG_DBG("tx slab num_blocks = %d",
682 (uint32_t)i2s_cfg->mem_slab->info.num_blocks);
683 LOG_DBG("tx slab block_size = %d",
684 (uint32_t)i2s_cfg->mem_slab->info.block_size);
685 LOG_DBG("tx slab buffer = 0x%x",
686 (uint32_t)i2s_cfg->mem_slab->buffer);
687
688 /* set bit clock divider */
689 SAI_TxSetConfig(base, &config);
690 dev_data->tx.start_channel = config.startChannel;
691 /* Disable the channel FIFO */
692 base->TCR3 &= ~I2S_TCR3_TCE_MASK;
693 SAI_TxSetBitClockRate(base, mclk,
694 i2s_cfg->frame_clk_freq,
695 word_size_bits,
696 i2s_cfg->channels);
697 LOG_DBG("tx start_channel = %d", dev_data->tx.start_channel);
698 /*set up dma settings*/
699 dev_data->tx.dma_cfg.source_data_size = word_size_bits / 8;
700 dev_data->tx.dma_cfg.dest_data_size = word_size_bits / 8;
701 dev_data->tx.dma_cfg.source_burst_length =
702 i2s_cfg->word_size / 8;
703 dev_data->tx.dma_cfg.dest_burst_length =
704 i2s_cfg->word_size / 8;
705 dev_data->tx.dma_cfg.user_data = (void *)dev;
706 dev_data->tx.state = I2S_STATE_READY;
707 } else {
708 /* For RX, DMA reads from FIFO whenever data present */
709 config.fifo.fifoWatermark = 0;
710
711 memcpy(&dev_data->rx.cfg, i2s_cfg, sizeof(struct i2s_config));
712 LOG_DBG("rx slab free_list = 0x%x",
713 (uint32_t)i2s_cfg->mem_slab->free_list);
714 LOG_DBG("rx slab num_blocks = %d",
715 (uint32_t)i2s_cfg->mem_slab->info.num_blocks);
716 LOG_DBG("rx slab block_size = %d",
717 (uint32_t)i2s_cfg->mem_slab->info.block_size);
718 LOG_DBG("rx slab buffer = 0x%x",
719 (uint32_t)i2s_cfg->mem_slab->buffer);
720
721 /* set bit clock divider */
722 SAI_RxSetConfig(base, &config);
723 dev_data->rx.start_channel = config.startChannel;
724 SAI_RxSetBitClockRate(base, mclk,
725 i2s_cfg->frame_clk_freq,
726 word_size_bits,
727 i2s_cfg->channels);
728 LOG_DBG("rx start_channel = %d", dev_data->rx.start_channel);
729 /*set up dma settings*/
730 dev_data->rx.dma_cfg.source_data_size = word_size_bits / 8;
731 dev_data->rx.dma_cfg.dest_data_size = word_size_bits / 8;
732 dev_data->rx.dma_cfg.source_burst_length =
733 i2s_cfg->word_size / 8;
734 dev_data->rx.dma_cfg.dest_burst_length =
735 i2s_cfg->word_size / 8;
736 dev_data->rx.dma_cfg.user_data = (void *)dev;
737 dev_data->rx.state = I2S_STATE_READY;
738 }
739
740 return 0;
741 }
742
i2s_mcux_config_get(const struct device * dev,enum i2s_dir dir)743 const struct i2s_config *i2s_mcux_config_get(const struct device *dev,
744 enum i2s_dir dir)
745 {
746 struct i2s_dev_data *dev_data = dev->data;
747
748 if (dir == I2S_DIR_RX) {
749 return &dev_data->rx.cfg;
750 }
751
752 return &dev_data->tx.cfg;
753 }
754
i2s_tx_stream_start(const struct device * dev)755 static int i2s_tx_stream_start(const struct device *dev)
756 {
757 int ret = 0;
758 void *buffer;
759 struct i2s_dev_data *dev_data = dev->data;
760 struct stream *strm = &dev_data->tx;
761 const struct device *dev_dma = dev_data->dev_dma;
762 const struct i2s_mcux_config *dev_cfg = dev->config;
763 I2S_Type *base = (I2S_Type *)dev_cfg->base;
764
765 /* retrieve buffer from input queue */
766 ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
767 if (ret != 0) {
768 LOG_ERR("No buffer in input queue to start");
769 return -EIO;
770 }
771
772 LOG_DBG("tx stream start");
773
774 /* Driver keeps track of how many DMA blocks can be loaded to the DMA */
775 strm->free_tx_dma_blocks = MAX_TX_DMA_BLOCKS;
776
777 /* Configure the DMA with the first TX block */
778 struct dma_block_config *blk_cfg = &strm->dma_block;
779
780 memset(blk_cfg, 0, sizeof(struct dma_block_config));
781
782 uint32_t data_path = strm->start_channel;
783
784 blk_cfg->dest_address = (uint32_t)&base->TDR[data_path];
785 blk_cfg->source_address = (uint32_t)buffer;
786 blk_cfg->block_size = strm->cfg.block_size;
787 blk_cfg->dest_scatter_en = 1;
788
789 strm->dma_cfg.block_count = 1;
790
791 strm->dma_cfg.head_block = &strm->dma_block;
792 strm->dma_cfg.user_data = (void *)dev;
793
794
795 (strm->free_tx_dma_blocks)--;
796 dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg);
797
798 /* put buffer in output queue */
799 ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
800 if (ret != 0) {
801 LOG_ERR("failed to put buffer in output queue");
802 return ret;
803 }
804
805 uint8_t blocks_queued;
806
807 ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
808 if (ret) {
809 LOG_ERR("i2s_tx_reload_multiple_dma_blocks() failed (%d)", ret);
810 return ret;
811 }
812
813 ret = dma_start(dev_dma, strm->dma_channel);
814 if (ret < 0) {
815 LOG_ERR("dma_start failed (%d)", ret);
816 return ret;
817 }
818
819 /* Enable DMA enable bit */
820 SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
821
822 /* Enable the channel FIFO */
823 base->TCR3 |= I2S_TCR3_TCE(1UL << strm->start_channel);
824
825 /* Enable SAI Tx clock */
826 SAI_TxEnable(base, true);
827
828 return 0;
829 }
830
i2s_rx_stream_start(const struct device * dev)831 static int i2s_rx_stream_start(const struct device *dev)
832 {
833 int ret = 0;
834 void *buffer;
835 struct i2s_dev_data *dev_data = dev->data;
836 struct stream *strm = &dev_data->rx;
837 const struct device *dev_dma = dev_data->dev_dma;
838 const struct i2s_mcux_config *dev_cfg = dev->config;
839 I2S_Type *base = (I2S_Type *)dev_cfg->base;
840 uint8_t num_of_bufs;
841
842 num_of_bufs = k_mem_slab_num_free_get(strm->cfg.mem_slab);
843
844 /*
845 * Need at least NUM_DMA_BLOCKS_RX_PREP buffers on the RX memory slab
846 * for reliable DMA reception.
847 */
848 if (num_of_bufs < NUM_DMA_BLOCKS_RX_PREP) {
849 return -EINVAL;
850 }
851
852 /* allocate 1st receive buffer from SLAB */
853 ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer,
854 K_NO_WAIT);
855 if (ret != 0) {
856 LOG_DBG("buffer alloc from mem_slab failed (%d)", ret);
857 return ret;
858 }
859
860 /* Configure DMA block */
861 struct dma_block_config *blk_cfg = &strm->dma_block;
862
863 memset(blk_cfg, 0, sizeof(struct dma_block_config));
864
865 uint32_t data_path = strm->start_channel;
866
867 blk_cfg->dest_address = (uint32_t)buffer;
868 blk_cfg->source_address = (uint32_t)&base->RDR[data_path];
869 blk_cfg->block_size = strm->cfg.block_size;
870
871 blk_cfg->source_gather_en = 1;
872
873 strm->dma_cfg.block_count = 1;
874 strm->dma_cfg.head_block = &strm->dma_block;
875 strm->dma_cfg.user_data = (void *)dev;
876
877 dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg);
878
879 /* put buffer in input queue */
880 ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
881 if (ret != 0) {
882 LOG_ERR("failed to put buffer in input queue, ret1 %d", ret);
883 return ret;
884 }
885
886 /* prep DMA for each of remaining (NUM_DMA_BLOCKS_RX_PREP-1) buffers */
887 for (int i = 0; i < NUM_DMA_BLOCKS_RX_PREP - 1; i++) {
888
889 /* allocate receive buffer from SLAB */
890 ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer,
891 K_NO_WAIT);
892 if (ret != 0) {
893 LOG_ERR("buffer alloc from mem_slab failed (%d)", ret);
894 return ret;
895 }
896
897 ret = dma_reload(dev_dma, strm->dma_channel,
898 (uint32_t)&base->RDR[data_path],
899 (uint32_t)buffer, blk_cfg->block_size);
900 if (ret != 0) {
901 LOG_ERR("dma_reload() failed with error 0x%x", ret);
902 return ret;
903 }
904
905 /* put buffer in input queue */
906 ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
907 if (ret != 0) {
908 LOG_ERR("failed to put buffer in input queue, ret2 %d",
909 ret);
910 return ret;
911 }
912 }
913
914 LOG_DBG("Starting DMA Ch%u", strm->dma_channel);
915 ret = dma_start(dev_dma, strm->dma_channel);
916 if (ret < 0) {
917 LOG_ERR("Failed to start DMA Ch%d (%d)", strm->dma_channel,
918 ret);
919 return ret;
920 }
921
922 /* Enable DMA enable bit */
923 SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
924
925 /* Enable the channel FIFO */
926 base->RCR3 |= I2S_RCR3_RCE(1UL << strm->start_channel);
927
928 /* Enable SAI Rx clock */
929 SAI_RxEnable(base, true);
930
931 return 0;
932 }
933
i2s_mcux_trigger(const struct device * dev,enum i2s_dir dir,enum i2s_trigger_cmd cmd)934 static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
935 enum i2s_trigger_cmd cmd)
936 {
937 struct i2s_dev_data *dev_data = dev->data;
938 struct stream *strm;
939 unsigned int key;
940 int ret = 0;
941
942 if (dir == I2S_DIR_BOTH) {
943 return -ENOSYS;
944 }
945
946 strm = (dir == I2S_DIR_TX) ? &dev_data->tx : &dev_data->rx;
947
948 key = irq_lock();
949 switch (cmd) {
950 case I2S_TRIGGER_START:
951 if (strm->state != I2S_STATE_READY) {
952 LOG_ERR("START trigger: invalid state %u",
953 strm->state);
954 ret = -EIO;
955 break;
956 }
957
958 if (dir == I2S_DIR_TX) {
959 ret = i2s_tx_stream_start(dev);
960 } else {
961 ret = i2s_rx_stream_start(dev);
962 }
963
964 if (ret < 0) {
965 LOG_DBG("START trigger failed %d", ret);
966 ret = -EIO;
967 break;
968 }
969
970 strm->state = I2S_STATE_RUNNING;
971 strm->last_block = false;
972 break;
973
974 case I2S_TRIGGER_DROP:
975 if (strm->state == I2S_STATE_NOT_READY) {
976 LOG_ERR("DROP trigger: invalid state %d",
977 strm->state);
978 ret = -EIO;
979 break;
980 }
981
982 strm->state = I2S_STATE_READY;
983 if (dir == I2S_DIR_TX) {
984 i2s_tx_stream_disable(dev, true);
985 } else {
986 i2s_rx_stream_disable(dev, true, true);
987 }
988 break;
989
990 case I2S_TRIGGER_STOP:
991 if (strm->state != I2S_STATE_RUNNING) {
992 LOG_ERR("STOP trigger: invalid state %d", strm->state);
993 ret = -EIO;
994 break;
995 }
996
997 strm->state = I2S_STATE_STOPPING;
998 strm->last_block = true;
999 break;
1000
1001 case I2S_TRIGGER_DRAIN:
1002 if (strm->state != I2S_STATE_RUNNING) {
1003 LOG_ERR("DRAIN/STOP trigger: invalid state %d",
1004 strm->state);
1005 ret = -EIO;
1006 break;
1007 }
1008
1009 strm->state = I2S_STATE_STOPPING;
1010 break;
1011
1012 case I2S_TRIGGER_PREPARE:
1013 if (strm->state != I2S_STATE_ERROR) {
1014 LOG_ERR("PREPARE trigger: invalid state %d",
1015 strm->state);
1016 ret = -EIO;
1017 break;
1018 }
1019 strm->state = I2S_STATE_READY;
1020 if (dir == I2S_DIR_TX) {
1021 i2s_tx_stream_disable(dev, true);
1022 } else {
1023 i2s_rx_stream_disable(dev, true, true);
1024 }
1025 break;
1026
1027 default:
1028 LOG_ERR("Unsupported trigger command");
1029 ret = -EINVAL;
1030 }
1031
1032 irq_unlock(key);
1033 return ret;
1034 }
1035
i2s_mcux_read(const struct device * dev,void ** mem_block,size_t * size)1036 static int i2s_mcux_read(const struct device *dev, void **mem_block,
1037 size_t *size)
1038 {
1039 struct i2s_dev_data *dev_data = dev->data;
1040 struct stream *strm = &dev_data->rx;
1041 void *buffer;
1042 int status, ret = 0;
1043
1044 LOG_DBG("i2s_mcux_read");
1045 if (strm->state == I2S_STATE_NOT_READY) {
1046 LOG_ERR("invalid state %d", strm->state);
1047 return -EIO;
1048 }
1049
1050 status = k_msgq_get(&strm->out_queue, &buffer,
1051 SYS_TIMEOUT_MS(strm->cfg.timeout));
1052 if (status != 0) {
1053 if (strm->state == I2S_STATE_ERROR) {
1054 ret = -EIO;
1055 } else {
1056 LOG_DBG("need retry");
1057 ret = -EAGAIN;
1058 }
1059 return ret;
1060 }
1061
1062 *mem_block = buffer;
1063 *size = strm->cfg.block_size;
1064 return 0;
1065 }
1066
i2s_mcux_write(const struct device * dev,void * mem_block,size_t size)1067 static int i2s_mcux_write(const struct device *dev, void *mem_block,
1068 size_t size)
1069 {
1070 struct i2s_dev_data *dev_data = dev->data;
1071 struct stream *strm = &dev_data->tx;
1072 int ret;
1073
1074 LOG_DBG("i2s_mcux_write");
1075 if (strm->state != I2S_STATE_RUNNING &&
1076 strm->state != I2S_STATE_READY) {
1077 LOG_ERR("invalid state (%d)", strm->state);
1078 return -EIO;
1079 }
1080
1081 ret = k_msgq_put(&strm->in_queue, &mem_block,
1082 SYS_TIMEOUT_MS(strm->cfg.timeout));
1083 if (ret) {
1084 LOG_DBG("k_msgq_put returned code %d", ret);
1085 return ret;
1086 }
1087
1088 return ret;
1089 }
1090
sai_driver_irq(const struct device * dev)1091 static void sai_driver_irq(const struct device *dev)
1092 {
1093 const struct i2s_mcux_config *dev_cfg = dev->config;
1094 I2S_Type *base = (I2S_Type *)dev_cfg->base;
1095
1096 if ((base->TCSR & I2S_TCSR_FEF_MASK) == I2S_TCSR_FEF_MASK) {
1097 /* Clear FIFO error flag to continue transfer */
1098 SAI_TxClearStatusFlags(base, I2S_TCSR_FEF_MASK);
1099
1100 /* Reset FIFO for safety */
1101 SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO);
1102
1103 LOG_DBG("sai tx error occurred");
1104 }
1105
1106 if ((base->RCSR & I2S_RCSR_FEF_MASK) == I2S_RCSR_FEF_MASK) {
1107 /* Clear FIFO error flag to continue transfer */
1108 SAI_RxClearStatusFlags(base, I2S_RCSR_FEF_MASK);
1109
1110 /* Reset FIFO for safety */
1111 SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO);
1112
1113 LOG_DBG("sai rx error occurred");
1114 }
1115 }
1116
1117 /* clear IRQ sources atm */
i2s_mcux_isr(void * arg)1118 static void i2s_mcux_isr(void *arg)
1119 {
1120 struct device *dev = (struct device *)arg;
1121 const struct i2s_mcux_config *dev_cfg = dev->config;
1122 I2S_Type *base = (I2S_Type *)dev_cfg->base;
1123
1124 if ((base->RCSR & I2S_TCSR_FEF_MASK) == I2S_TCSR_FEF_MASK) {
1125 sai_driver_irq(dev);
1126 }
1127
1128 if ((base->TCSR & I2S_RCSR_FEF_MASK) == I2S_RCSR_FEF_MASK) {
1129 sai_driver_irq(dev);
1130 }
1131 /*
1132 * Add for ARM errata 838869, affects Cortex-M4,
1133 * Cortex-M4F Store immediate overlapping exception return operation
1134 * might vector to incorrect interrupt
1135 */
1136 #if defined __CORTEX_M && (__CORTEX_M == 4U)
1137 barrier_dsync_fence_full();
1138 #endif
1139 }
1140
audio_clock_settings(const struct device * dev)1141 static void audio_clock_settings(const struct device *dev)
1142 {
1143 clock_audio_pll_config_t audioPllConfig;
1144 const struct i2s_mcux_config *dev_cfg = dev->config;
1145 uint32_t clock_name = (uint32_t) dev_cfg->clk_sub_sys;
1146
1147 /*Clock setting for SAI*/
1148 imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src,
1149 dev_cfg->clk_pre_div, dev_cfg->clk_src_div);
1150
1151 #ifdef CONFIG_SOC_SERIES_IMX_RT11XX
1152 audioPllConfig.loopDivider = dev_cfg->pll_lp;
1153 audioPllConfig.postDivider = dev_cfg->pll_pd;
1154 audioPllConfig.numerator = dev_cfg->pll_num;
1155 audioPllConfig.denominator = dev_cfg->pll_den;
1156 audioPllConfig.ssEnable = false;
1157 #elif defined CONFIG_SOC_SERIES_IMX_RT10XX
1158 audioPllConfig.src = dev_cfg->pll_src;
1159 audioPllConfig.loopDivider = dev_cfg->pll_lp;
1160 audioPllConfig.postDivider = dev_cfg->pll_pd;
1161 audioPllConfig.numerator = dev_cfg->pll_num;
1162 audioPllConfig.denominator = dev_cfg->pll_den;
1163 #else
1164 #error Initialize SOC Series-specific clock_audio_pll_config_t
1165 #endif /* CONFIG_SOC_SERIES */
1166
1167 CLOCK_InitAudioPll(&audioPllConfig);
1168 }
1169
i2s_mcux_initialize(const struct device * dev)1170 static int i2s_mcux_initialize(const struct device *dev)
1171 {
1172 const struct i2s_mcux_config *dev_cfg = dev->config;
1173 I2S_Type *base = (I2S_Type *)dev_cfg->base;
1174 struct i2s_dev_data *dev_data = dev->data;
1175 uint32_t mclk;
1176 int err;
1177
1178 if (!dev_data->dev_dma) {
1179 LOG_ERR("DMA device not found");
1180 return -ENODEV;
1181 }
1182
1183 /* Initialize the buffer queues */
1184 k_msgq_init(&dev_data->tx.in_queue, (char *)dev_data->tx_in_msgs,
1185 sizeof(void *), CONFIG_I2S_TX_BLOCK_COUNT);
1186 k_msgq_init(&dev_data->rx.in_queue, (char *)dev_data->rx_in_msgs,
1187 sizeof(void *), CONFIG_I2S_RX_BLOCK_COUNT);
1188 k_msgq_init(&dev_data->tx.out_queue, (char *)dev_data->tx_out_msgs,
1189 sizeof(void *), CONFIG_I2S_TX_BLOCK_COUNT);
1190 k_msgq_init(&dev_data->rx.out_queue, (char *)dev_data->rx_out_msgs,
1191 sizeof(void *), CONFIG_I2S_RX_BLOCK_COUNT);
1192
1193 /* register ISR */
1194 dev_cfg->irq_connect(dev);
1195 /* pinctrl */
1196 err = pinctrl_apply_state(dev_cfg->pinctrl, PINCTRL_STATE_DEFAULT);
1197 if (err) {
1198 LOG_ERR("mclk pinctrl setup failed (%d)", err);
1199 return err;
1200 }
1201
1202 /*clock configuration*/
1203 audio_clock_settings(dev);
1204
1205 SAI_Init(base);
1206
1207 dev_data->tx.state = I2S_STATE_NOT_READY;
1208 dev_data->rx.state = I2S_STATE_NOT_READY;
1209
1210 #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
1211 (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
1212 (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
1213 sai_master_clock_t mclkConfig = {
1214 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
1215 .mclkOutputEnable = true,
1216 #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && \
1217 (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
1218 .mclkSource = kSAI_MclkSourceSysclk,
1219 #endif
1220 #endif
1221 };
1222 #endif
1223
1224 get_mclk_rate(dev, &mclk);
1225 /* master clock configurations */
1226 #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
1227 (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
1228 (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
1229 #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
1230 (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
1231 mclkConfig.mclkHz = mclk;
1232 mclkConfig.mclkSourceClkHz = mclk;
1233 #endif
1234 SAI_SetMasterClockConfig(base, &mclkConfig);
1235 #endif
1236
1237 LOG_INF("Device %s initialized", dev->name);
1238
1239 return 0;
1240 }
1241
1242 static const struct i2s_driver_api i2s_mcux_driver_api = {
1243 .configure = i2s_mcux_config,
1244 .read = i2s_mcux_read,
1245 .write = i2s_mcux_write,
1246 .config_get = i2s_mcux_config_get,
1247 .trigger = i2s_mcux_trigger,
1248 };
1249
1250 #define I2S_MCUX_INIT(i2s_id) \
1251 static void i2s_irq_connect_##i2s_id(const struct device *dev); \
1252 \
1253 PINCTRL_DT_INST_DEFINE(i2s_id); \
1254 \
1255 static const struct i2s_mcux_config i2s_##i2s_id##_config = { \
1256 .base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id), \
1257 .clk_src = \
1258 DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(i2s_id), \
1259 0, bits), \
1260 .clk_pre_div = DT_INST_PROP(i2s_id, pre_div), \
1261 .clk_src_div = DT_INST_PROP(i2s_id, podf), \
1262 .pll_src = \
1263 DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
1264 pll_clocks, src, value), \
1265 .pll_lp = \
1266 DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
1267 pll_clocks, lp, value), \
1268 .pll_pd = \
1269 DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
1270 pll_clocks, pd, value), \
1271 .pll_num = \
1272 DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
1273 pll_clocks, num, value), \
1274 .pll_den = \
1275 DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
1276 pll_clocks, den, value), \
1277 .mclk_pin_mask = \
1278 DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), \
1279 pinmuxes, 0, function), \
1280 .mclk_pin_offset = \
1281 DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), \
1282 pinmuxes, 0, pin), \
1283 .clk_sub_sys = (clock_control_subsys_t) \
1284 DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \
1285 .ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)), \
1286 .irq_connect = i2s_irq_connect_##i2s_id, \
1287 .pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id), \
1288 .tx_sync_mode = \
1289 DT_INST_PROP(i2s_id, nxp_tx_sync_mode), \
1290 .rx_sync_mode = \
1291 DT_INST_PROP(i2s_id, nxp_rx_sync_mode), \
1292 .tx_channel = DT_INST_PROP(i2s_id, nxp_tx_channel), \
1293 }; \
1294 \
1295 static struct i2s_dev_data i2s_##i2s_id##_data = { \
1296 .dev_dma = DEVICE_DT_GET( \
1297 DT_INST_DMAS_CTLR_BY_NAME(i2s_id, rx)), \
1298 .tx = { \
1299 .dma_channel = \
1300 DT_INST_PROP(i2s_id, nxp_tx_dma_channel), \
1301 .dma_cfg = { \
1302 .source_burst_length = \
1303 CONFIG_I2S_EDMA_BURST_SIZE, \
1304 .dest_burst_length = \
1305 CONFIG_I2S_EDMA_BURST_SIZE, \
1306 .dma_callback = i2s_dma_tx_callback, \
1307 .complete_callback_en = 1, \
1308 .error_callback_en = 1, \
1309 .block_count = 1, \
1310 .head_block = \
1311 &i2s_##i2s_id##_data.tx.dma_block, \
1312 .channel_direction = MEMORY_TO_PERIPHERAL, \
1313 .dma_slot = \
1314 DT_INST_DMAS_CELL_BY_NAME(i2s_id, \
1315 tx, source), \
1316 }, \
1317 }, \
1318 .rx = { \
1319 .dma_channel = \
1320 DT_INST_PROP(i2s_id, nxp_rx_dma_channel), \
1321 .dma_cfg = { \
1322 .source_burst_length = \
1323 CONFIG_I2S_EDMA_BURST_SIZE, \
1324 .dest_burst_length = \
1325 CONFIG_I2S_EDMA_BURST_SIZE, \
1326 .dma_callback = i2s_dma_rx_callback, \
1327 .complete_callback_en = 1, \
1328 .error_callback_en = 1, \
1329 .block_count = 1, \
1330 .head_block = \
1331 &i2s_##i2s_id##_data.rx.dma_block, \
1332 .channel_direction = PERIPHERAL_TO_MEMORY, \
1333 .dma_slot = \
1334 DT_INST_DMAS_CELL_BY_NAME(i2s_id, \
1335 rx, source), \
1336 }, \
1337 }, \
1338 }; \
1339 \
1340 DEVICE_DT_INST_DEFINE(i2s_id, &i2s_mcux_initialize, NULL, \
1341 &i2s_##i2s_id##_data, &i2s_##i2s_id##_config, \
1342 POST_KERNEL, \
1343 CONFIG_I2S_INIT_PRIORITY, &i2s_mcux_driver_api); \
1344 \
1345 static void i2s_irq_connect_##i2s_id(const struct device *dev) \
1346 { \
1347 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(i2s_id, 0, irq), \
1348 DT_INST_IRQ_BY_IDX(i2s_id, 0, priority), \
1349 i2s_mcux_isr, \
1350 DEVICE_DT_INST_GET(i2s_id), 0); \
1351 irq_enable(DT_INST_IRQN(i2s_id)); \
1352 }
1353
1354 DT_INST_FOREACH_STATUS_OKAY(I2S_MCUX_INIT)
1355
