1/* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <nordic/nrf_common.dtsi> 9#include <zephyr/dt-bindings/adc/nrf-saadc.h> 10#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h> 11#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h> 12#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h> 13#include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h> 14 15/delete-node/ &sw_pwm; 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpuapp: cpu@2 { 26 compatible = "arm,cortex-m33"; 27 reg = <2>; 28 device_type = "cpu"; 29 clock-frequency = <DT_FREQ_M(320)>; 30 }; 31 32 cpurad: cpu@3 { 33 compatible = "arm,cortex-m33"; 34 reg = <3>; 35 device_type = "cpu"; 36 clock-frequency = <DT_FREQ_M(256)>; 37 }; 38 39 cpuppr: cpu@d { 40 compatible = "nordic,vpr"; 41 reg = <13>; 42 device_type = "cpu"; 43 clock-frequency = <DT_FREQ_M(16)>; 44 riscv,isa = "rv32emc"; 45 nordic,bus-width = <32>; 46 47 cpuppr_vevif_rx: mailbox { 48 compatible = "nordic,nrf-vevif-task-rx"; 49 status = "disabled"; 50 interrupt-parent = <&cpuppr_clic>; 51 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, 52 <1 NRF_DEFAULT_IRQ_PRIORITY>, 53 <2 NRF_DEFAULT_IRQ_PRIORITY>, 54 <3 NRF_DEFAULT_IRQ_PRIORITY>, 55 <4 NRF_DEFAULT_IRQ_PRIORITY>, 56 <5 NRF_DEFAULT_IRQ_PRIORITY>, 57 <6 NRF_DEFAULT_IRQ_PRIORITY>, 58 <7 NRF_DEFAULT_IRQ_PRIORITY>, 59 <8 NRF_DEFAULT_IRQ_PRIORITY>, 60 <9 NRF_DEFAULT_IRQ_PRIORITY>, 61 <10 NRF_DEFAULT_IRQ_PRIORITY>, 62 <11 NRF_DEFAULT_IRQ_PRIORITY>, 63 <12 NRF_DEFAULT_IRQ_PRIORITY>, 64 <13 NRF_DEFAULT_IRQ_PRIORITY>, 65 <14 NRF_DEFAULT_IRQ_PRIORITY>, 66 <15 NRF_DEFAULT_IRQ_PRIORITY>; 67 #mbox-cells = <1>; 68 nordic,tasks = <16>; 69 nordic,tasks-mask = <0x0000fff0>; 70 }; 71 }; 72 }; 73 74 reserved-memory { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 78 suit_storage_partition: memory@e6b7000 { 79 reg = <0xe6b7000 DT_SIZE_K(40)>; 80 }; 81 }; 82 83 clocks { 84 hfxo: hfxo { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <DT_FREQ_M(32)>; 88 }; 89 90 fll16m: fll16m { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <DT_FREQ_M(16)>; 94 }; 95 96 hsfll120: hsfll120 { 97 compatible = "nordic,nrf-hsfll-global"; 98 clocks = <&fll16m>; 99 #clock-cells = <0>; 100 clock-frequency = <320000000>; 101 supported-clock-frequencies = <64000000 102 128000000 103 256000000 104 320000000>; 105 }; 106 }; 107 108 soc { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 112 mram1x: mram@e000000 { 113 compatible = "nordic,mram"; 114 reg = <0xe000000 DT_SIZE_K(8192)>; 115 erase-block-size = <4096>; 116 write-block-size = <16>; 117 }; 118 119 cpuapp_uicr: uicr@fff8000 { 120 compatible = "nordic,nrf-uicr-v2"; 121 reg = <0xfff8000 DT_SIZE_K(2)>; 122 domain = <2>; 123 }; 124 125 cpurad_uicr: uicr@fffa000 { 126 compatible = "nordic,nrf-uicr-v2"; 127 reg = <0xfffa000 DT_SIZE_K(2)>; 128 domain = <3>; 129 }; 130 131 ficr: ficr@fffe000 { 132 compatible = "nordic,nrf-ficr"; 133 reg = <0xfffe000 DT_SIZE_K(2)>; 134 #nordic,ficr-cells = <1>; 135 }; 136 137 cpuapp_ram0: sram@22000000 { 138 compatible = "mmio-sram"; 139 reg = <0x22000000 DT_SIZE_K(32)>; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 ranges = <0x0 0x22000000 0x8000>; 143 }; 144 145 cpurad_ram0: sram@23000000 { 146 compatible = "mmio-sram"; 147 reg = <0x23000000 DT_SIZE_K(192)>; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0x0 0x23000000 0x30000>; 151 }; 152 153 cpurad_ram1: sram@23040000 { 154 compatible = "mmio-sram"; 155 reg = <0x23040000 DT_SIZE_K(32)>; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges = <0x0 0x23040000 0x8000>; 159 }; 160 161 cpuapp_peripherals: peripheral@52000000 { 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0x0 0x52000000 0x1000000>; 165 166 cpuapp_hsfll: clock@d000 { 167 compatible = "nordic,nrf-hsfll-local"; 168 #clock-cells = <0>; 169 reg = <0xd000 0x1000>; 170 clocks = <&fll16m>; 171 clock-frequency = <DT_FREQ_M(320)>; 172 nordic,ficrs = 173 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, 174 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, 175 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; 176 nordic,ficr-names = "vsup", "coarse", "fine"; 177 }; 178 179 cpuapp_ipct: ipct@13000 { 180 compatible = "nordic,nrf-ipct-local"; 181 reg = <0x13000 0x1000>; 182 status = "disabled"; 183 channels = <4>; 184 interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, 185 <65 NRF_DEFAULT_IRQ_PRIORITY>; 186 }; 187 188 cpuapp_wdt010: watchdog@14000 { 189 compatible = "nordic,nrf-wdt"; 190 reg = <0x14000 0x1000>; 191 status = "disabled"; 192 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 193 }; 194 195 cpuapp_wdt011: watchdog@15000 { 196 compatible = "nordic,nrf-wdt"; 197 reg = <0x15000 0x1000>; 198 status = "disabled"; 199 interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>; 200 }; 201 202 cpuapp_ieee802154: ieee802154 { 203 compatible = "nordic,nrf-ieee802154"; 204 status = "disabled"; 205 }; 206 207 cpuapp_resetinfo: resetinfo@1e000 { 208 compatible = "nordic,nrf-resetinfo"; 209 reg = <0x1e000 0x1000>; 210 }; 211 }; 212 213 cpurad_peripherals: peripheral@53000000 { 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges = <0x0 0x53000000 0x1000000>; 217 218 cpurad_hsfll: clock@d000 { 219 compatible = "nordic,nrf-hsfll-local"; 220 #clock-cells = <0>; 221 reg = <0xd000 0x1000>; 222 clocks = <&fll16m>; 223 clock-frequency = <DT_FREQ_M(256)>; 224 nordic,ficrs = 225 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, 226 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, 227 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; 228 nordic,ficr-names = "vsup", "coarse", "fine"; 229 }; 230 231 cpurad_wdt010: watchdog@13000 { 232 compatible = "nordic,nrf-wdt"; 233 reg = <0x13000 0x1000>; 234 status = "disabled"; 235 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 236 }; 237 238 cpurad_wdt011: watchdog@14000 { 239 compatible = "nordic,nrf-wdt"; 240 reg = <0x14000 0x1000>; 241 status = "disabled"; 242 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 243 }; 244 245 cpurad_resetinfo: resetinfo@1e000 { 246 compatible = "nordic,nrf-resetinfo"; 247 reg = <0x1e000 0x1000>; 248 }; 249 250 dppic020: dppic@22000 { 251 compatible = "nordic,nrf-dppic-local"; 252 reg = <0x22000 0x1000>; 253 status = "disabled"; 254 }; 255 256 cpurad_ipct: ipct@24000 { 257 compatible = "nordic,nrf-ipct-local"; 258 reg = <0x24000 0x1000>; 259 status = "disabled"; 260 channels = <8>; 261 interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, 262 <65 NRF_DEFAULT_IRQ_PRIORITY>; 263 }; 264 265 egu020: egu@25000 { 266 compatible = "nordic,nrf-egu"; 267 reg = <0x25000 0x1000>; 268 status = "disabled"; 269 interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; 270 }; 271 272 timer020: timer@28000 { 273 compatible = "nordic,nrf-timer"; 274 reg = <0x28000 0x1000>; 275 status = "disabled"; 276 cc-num = <8>; 277 interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; 278 max-bit-width = <32>; 279 clocks = <&hfxo>; 280 prescaler = <0>; 281 }; 282 283 timer021: timer@29000 { 284 compatible = "nordic,nrf-timer"; 285 reg = <0x29000 0x1000>; 286 status = "disabled"; 287 cc-num = <8>; 288 interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; 289 max-bit-width = <32>; 290 clocks = <&hfxo>; 291 prescaler = <0>; 292 }; 293 294 timer022: timer@2a000 { 295 compatible = "nordic,nrf-timer"; 296 reg = <0x2a000 0x1000>; 297 status = "disabled"; 298 cc-num = <8>; 299 interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; 300 max-bit-width = <32>; 301 clocks = <&hfxo>; 302 prescaler = <0>; 303 }; 304 305 rtc: rtc@2b000 { 306 compatible = "nordic,nrf-rtc"; 307 reg = <0x2b000 0x1000>; 308 status = "disabled"; 309 cc-num = <4>; 310 clock-frequency = <32768>; 311 interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; 312 prescaler = <1>; 313 }; 314 315 radio: radio@2c000 { 316 compatible = "nordic,nrf-radio"; 317 reg = <0x2c000 0x1000>; 318 status = "disabled"; 319 ble-2mbps-supported; 320 ble-coded-phy-supported; 321 dfe-supported; 322 ieee802154-supported; 323 interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; 324 325 cpurad_ieee802154: ieee802154 { 326 compatible = "nordic,nrf-ieee802154"; 327 status = "disabled"; 328 }; 329 }; 330 331 ccm030: ccm@3a000 { 332 compatible = "nordic,nrf-ccm"; 333 reg = <0x3a000 0x1000>; 334 interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>; 335 status = "disabled"; 336 }; 337 338 ecb030: ecb@3b000 { 339 compatible = "nordic,nrf-ecb"; 340 reg = <0x3b000 0x1000>; 341 interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; 342 status = "disabled"; 343 }; 344 345 ccm031: ccm@3c000 { 346 compatible = "nordic,nrf-ccm"; 347 reg = <0x3c000 0x1000>; 348 interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; 349 status = "disabled"; 350 }; 351 352 ecb031: ecb@3d000 { 353 compatible = "nordic,nrf-ecb"; 354 reg = <0x3d000 0x1000>; 355 status = "disabled"; 356 interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; 357 }; 358 }; 359 360 global_peripherals: peripheral@5f000000 { 361 #address-cells = <1>; 362 #size-cells = <1>; 363 ranges = <0x0 0x5f000000 0x1000000>; 364 365 usbhs: usbhs@86000 { 366 compatible = "nordic,nrf-usbhs", "snps,dwc2"; 367 reg = <0x86000 0x1000>, <0x2f700000 0x40000>; 368 reg-names = "wrapper", "core"; 369 interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>; 370 num-in-eps = <8>; 371 num-out-eps = <10>; 372 ghwcfg1 = <0xaa555000>; 373 ghwcfg2 = <0x22abfc72>; 374 ghwcfg4 = <0x1e10aa60>; 375 status = "disabled"; 376 }; 377 378 exmif: exmif@95000 { 379 compatible = "nordic,nrf-exmif", "snps,designware-ssi"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <0x95000 0x500 0x95500 0xb00>; 383 reg-names = "wrapper", "core"; 384 interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>; 385 clock-frequency = <DT_FREQ_M(400)>; 386 fifo-depth = <32>; 387 status = "disabled"; 388 }; 389 390 cpusec_bellboard: mailbox@99000 { 391 reg = <0x99000 0x1000>; 392 status = "disabled"; 393 #mbox-cells = <1>; 394 }; 395 396 cpuapp_bellboard: mailbox@9a000 { 397 reg = <0x9a000 0x1000>; 398 status = "disabled"; 399 #mbox-cells = <1>; 400 }; 401 402 cpurad_bellboard: mailbox@9b000 { 403 reg = <0x9b000 0x1000>; 404 status = "disabled"; 405 #mbox-cells = <1>; 406 }; 407 408 cpucell_bellboard: mailbox@9c000 { 409 reg = <0x9c000 0x1000>; 410 status = "disabled"; 411 #mbox-cells = <1>; 412 }; 413 414 canpll: clock-controller@8c2000{ 415 compatible = "nordic,nrf-auxpll"; 416 reg = <0x8c2000 0x1000>; 417 interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; 418 clocks = <&hfxo>; 419 #clock-cells = <0>; 420 nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>; 421 nordic,frequency = <0>; 422 nordic,out-div = <2>; 423 nordic,out-drive = <0>; 424 nordic,current-tune = <6>; 425 nordic,sdm-disable; 426 nordic,range = "high"; 427 status = "disabled"; 428 }; 429 430 cpusys_vevif_tx: mailbox@8c8000 { 431 compatible = "nordic,nrf-vevif-task-tx"; 432 reg = <0x8c8000 0x1000>; 433 status = "disabled"; 434 #mbox-cells = <1>; 435 nordic,tasks = <32>; 436 nordic,tasks-mask = <0xfffff0ff>; 437 }; 438 439 ipct120: ipct@8d1000 { 440 compatible = "nordic,nrf-ipct-global"; 441 reg = <0x8d1000 0x1000>; 442 status = "disabled"; 443 channels = <8>; 444 global-domain-id = <12>; 445 }; 446 447 dppic120: dppic@8e1000 { 448 compatible = "nordic,nrf-dppic-global"; 449 reg = <0x8e1000 0x1000>; 450 status = "disabled"; 451 }; 452 453 timer120: timer@8e2000 { 454 compatible = "nordic,nrf-timer"; 455 reg = <0x8e2000 0x1000>; 456 status = "disabled"; 457 cc-num = <6>; 458 interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; 459 max-bit-width = <32>; 460 clocks = <&hsfll120>; 461 prescaler = <0>; 462 }; 463 464 timer121: timer@8e3000 { 465 compatible = "nordic,nrf-timer"; 466 reg = <0x8e3000 0x1000>; 467 status = "disabled"; 468 cc-num = <6>; 469 interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; 470 max-bit-width = <32>; 471 clocks = <&hsfll120>; 472 prescaler = <0>; 473 }; 474 475 pwm120: pwm@8e4000 { 476 compatible = "nordic,nrf-pwm"; 477 reg = <0x8e4000 0x1000>; 478 status = "disabled"; 479 interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; 480 #pwm-cells = <3>; 481 }; 482 483 spi120: spi@8e6000 { 484 compatible = "nordic,nrf-spim"; 485 reg = <0x8e6000 0x1000>; 486 status = "disabled"; 487 easydma-maxcnt-bits = <15>; 488 interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; 489 max-frequency = <DT_FREQ_M(32)>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 rx-delay-supported; 493 rx-delay = <1>; 494 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, 495 <NRF_FUN_SPIS_SCK>; 496 }; 497 498 uart120: uart@8e6000 { 499 compatible = "nordic,nrf-uarte"; 500 reg = <0x8e6000 0x1000>; 501 status = "disabled"; 502 interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; 503 endtx-stoptx-supported; 504 frame-timeout-supported; 505 }; 506 507 spi121: spi@8e7000 { 508 compatible = "nordic,nrf-spim"; 509 reg = <0x8e7000 0x1000>; 510 status = "disabled"; 511 easydma-maxcnt-bits = <15>; 512 interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; 513 max-frequency = <DT_FREQ_M(32)>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 rx-delay-supported; 517 rx-delay = <1>; 518 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, 519 <NRF_FUN_SPIS_SCK>; 520 }; 521 522 cpuppr_vpr: vpr@908000 { 523 compatible = "nordic,nrf-vpr-coprocessor"; 524 reg = <0x908000 0x1000>; 525 status = "disabled"; 526 #address-cells = <1>; 527 #size-cells = <1>; 528 ranges = <0x0 0x908000 0x1000>; 529 530 cpuppr_vevif_tx: mailbox@0 { 531 compatible = "nordic,nrf-vevif-task-tx"; 532 reg = <0x0 0x1000>; 533 status = "disabled"; 534 #mbox-cells = <1>; 535 nordic,tasks = <16>; 536 nordic,tasks-mask = <0x0000fff0>; 537 }; 538 }; 539 540 ipct130: ipct@921000 { 541 compatible = "nordic,nrf-ipct-global"; 542 reg = <0x921000 0x1000>; 543 status = "disabled"; 544 channels = <8>; 545 global-domain-id = <13>; 546 }; 547 548 dppic130: dppic@922000 { 549 compatible = "nordic,nrf-dppic-global"; 550 reg = <0x922000 0x1000>; 551 status = "disabled"; 552 }; 553 554 rtc130: rtc@928000 { 555 compatible = "nordic,nrf-rtc"; 556 reg = <0x928000 0x1000>; 557 status = "disabled"; 558 cc-num = <4>; 559 clock-frequency = <32768>; 560 interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; 561 prescaler = <1>; 562 }; 563 564 rtc131: rtc@929000 { 565 compatible = "nordic,nrf-rtc"; 566 reg = <0x929000 0x1000>; 567 status = "disabled"; 568 cc-num = <4>; 569 clock-frequency = <32768>; 570 interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; 571 prescaler = <1>; 572 }; 573 574 wdt131: watchdog@92b000 { 575 compatible = "nordic,nrf-wdt"; 576 reg = <0x92b000 0x1000>; 577 status = "disabled"; 578 interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; 579 }; 580 581 wdt132: watchdog@92c000 { 582 compatible = "nordic,nrf-wdt"; 583 reg = <0x92c000 0x1000>; 584 status = "disabled"; 585 interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; 586 }; 587 588 gpiote130: gpiote@934000 { 589 compatible = "nordic,nrf-gpiote"; 590 reg = <0x934000 0x1000>; 591 status = "disabled"; 592 instance = <130>; 593 }; 594 595 gpiote131: gpiote@935000 { 596 compatible = "nordic,nrf-gpiote"; 597 reg = <0x935000 0x1000>; 598 status = "disabled"; 599 instance = <131>; 600 }; 601 602 gpio0: gpio@938000 { 603 compatible = "nordic,nrf-gpio"; 604 reg = <0x938000 0x200>; 605 status = "disabled"; 606 #gpio-cells = <2>; 607 gpio-controller; 608 gpiote-instance = <&gpiote130>; 609 ngpios = <13>; 610 port = <0>; 611 }; 612 613 gpio1: gpio@938200 { 614 compatible = "nordic,nrf-gpio"; 615 reg = <0x938200 0x200>; 616 status = "disabled"; 617 #gpio-cells = <2>; 618 gpio-controller; 619 gpiote-instance = <&gpiote130>; 620 ngpios = <12>; 621 port = <1>; 622 }; 623 624 gpio2: gpio@938400 { 625 compatible = "nordic,nrf-gpio"; 626 reg = <0x938400 0x200>; 627 status = "disabled"; 628 #gpio-cells = <2>; 629 gpio-controller; 630 gpiote-instance = <&gpiote130>; 631 ngpios = <12>; 632 port = <2>; 633 }; 634 635 gpio6: gpio@938c00 { 636 compatible = "nordic,nrf-gpio"; 637 reg = <0x938c00 0x200>; 638 status = "disabled"; 639 #gpio-cells = <2>; 640 gpio-controller; 641 ngpios = <14>; 642 port = <6>; 643 }; 644 645 gpio8: gpio@939000 { 646 compatible = "nordic,nrf-gpio"; 647 reg = <0x939000 0x200>; 648 status = "disabled"; 649 #gpio-cells = <2>; 650 gpio-controller; 651 ngpios = <5>; 652 port = <8>; 653 }; 654 655 gpio9: gpio@939200 { 656 compatible = "nordic,nrf-gpio"; 657 reg = <0x939200 0x200>; 658 status = "disabled"; 659 #gpio-cells = <2>; 660 gpio-controller; 661 gpiote-instance = <&gpiote130>; 662 ngpios = <6>; 663 port = <9>; 664 }; 665 666 gpio11: gpio@939600 { 667 compatible = "nordic,nrf-gpio"; 668 reg = <0x939600 0x200>; 669 status = "disabled"; 670 #gpio-cells = <2>; 671 gpio-controller; 672 gpiote-instance = <&gpiote131>; 673 ngpios = <8>; 674 port = <11>; 675 }; 676 677 dppic131: dppic@981000 { 678 compatible = "nordic,nrf-dppic-global"; 679 reg = <0x981000 0x1000>; 680 status = "disabled"; 681 }; 682 683 adc: adc@982000 { 684 compatible = "nordic,nrf-saadc"; 685 reg = <0x982000 0x1000>; 686 interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>; 687 status = "disabled"; 688 #io-channel-cells = <1>; 689 zephyr,pm-device-runtime-auto; 690 }; 691 692 comp: comparator@983000 { 693 /* 694 * Use compatible "nordic,nrf-comp" to configure as COMP 695 * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP 696 */ 697 compatible = "nordic,nrf-comp"; 698 reg = <0x983000 0x1000>; 699 status = "disabled"; 700 interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; 701 }; 702 703 temp: temperature-sensor@984000 { 704 compatible = "nordic,nrf-temp"; 705 reg = <0x984000 0x1000>; 706 interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; 707 status = "disabled"; 708 }; 709 710 dppic132: dppic@991000 { 711 compatible = "nordic,nrf-dppic-global"; 712 reg = <0x991000 0x1000>; 713 status = "disabled"; 714 }; 715 716 qdec130: qdec@994000 { 717 compatible = "nordic,nrf-qdec"; 718 reg = <0x994000 0x1000>; 719 status = "disabled"; 720 interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; 721 }; 722 723 qdec131: qdec@995000 { 724 compatible = "nordic,nrf-qdec"; 725 reg = <0x995000 0x1000>; 726 status = "disabled"; 727 interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; 728 }; 729 730 grtc: grtc@99c000 { 731 compatible = "nordic,nrf-grtc"; 732 reg = <0x99c000 0x1000>; 733 status = "disabled"; 734 cc-num = <16>; 735 }; 736 737 dppic133: dppic@9a1000 { 738 compatible = "nordic,nrf-dppic-global"; 739 reg = <0x9a1000 0x1000>; 740 status = "disabled"; 741 }; 742 743 timer130: timer@9a2000 { 744 compatible = "nordic,nrf-timer"; 745 reg = <0x9a2000 0x1000>; 746 status = "disabled"; 747 cc-num = <6>; 748 interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; 749 max-bit-width = <32>; 750 prescaler = <0>; 751 }; 752 753 timer131: timer@9a3000 { 754 compatible = "nordic,nrf-timer"; 755 reg = <0x9a3000 0x1000>; 756 status = "disabled"; 757 cc-num = <6>; 758 interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; 759 max-bit-width = <32>; 760 prescaler = <0>; 761 }; 762 763 pwm130: pwm@9a4000 { 764 compatible = "nordic,nrf-pwm"; 765 reg = <0x9a4000 0x1000>; 766 status = "disabled"; 767 interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; 768 #pwm-cells = <3>; 769 }; 770 771 i2c130: i2c@9a5000 { 772 compatible = "nordic,nrf-twim"; 773 reg = <0x9a5000 0x1000>; 774 status = "disabled"; 775 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 776 easydma-maxcnt-bits = <15>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 780 <NRF_FUN_TWIM_SCL>; 781 zephyr,pm-device-runtime-auto; 782 }; 783 784 spi130: spi@9a5000 { 785 compatible = "nordic,nrf-spim"; 786 reg = <0x9a5000 0x1000>; 787 status = "disabled"; 788 easydma-maxcnt-bits = <15>; 789 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 790 max-frequency = <DT_FREQ_M(8)>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 rx-delay-supported; 794 rx-delay = <1>; 795 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 796 <NRF_FUN_SPIM_SCK>, 797 <NRF_FUN_SPIS_MISO>, 798 <NRF_FUN_SPIS_SCK>; 799 }; 800 801 uart130: uart@9a5000 { 802 compatible = "nordic,nrf-uarte"; 803 reg = <0x9a5000 0x1000>; 804 status = "disabled"; 805 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 806 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 807 endtx-stoptx-supported; 808 frame-timeout-supported; 809 }; 810 811 i2c131: i2c@9a6000 { 812 compatible = "nordic,nrf-twim"; 813 reg = <0x9a6000 0x1000>; 814 status = "disabled"; 815 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 816 easydma-maxcnt-bits = <15>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 820 <NRF_FUN_TWIM_SCL>; 821 zephyr,pm-device-runtime-auto; 822 }; 823 824 spi131: spi@9a6000 { 825 compatible = "nordic,nrf-spim"; 826 reg = <0x9a6000 0x1000>; 827 status = "disabled"; 828 easydma-maxcnt-bits = <15>; 829 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 830 max-frequency = <DT_FREQ_M(8)>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 rx-delay-supported; 834 rx-delay = <1>; 835 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 836 <NRF_FUN_SPIM_SCK>, 837 <NRF_FUN_SPIS_MISO>, 838 <NRF_FUN_SPIS_SCK>; 839 }; 840 841 uart131: uart@9a6000 { 842 compatible = "nordic,nrf-uarte"; 843 reg = <0x9a6000 0x1000>; 844 status = "disabled"; 845 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 846 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 847 endtx-stoptx-supported; 848 frame-timeout-supported; 849 }; 850 851 dppic134: dppic@9b1000 { 852 compatible = "nordic,nrf-dppic-global"; 853 reg = <0x9b1000 0x1000>; 854 status = "disabled"; 855 }; 856 857 timer132: timer@9b2000 { 858 compatible = "nordic,nrf-timer"; 859 reg = <0x9b2000 0x1000>; 860 status = "disabled"; 861 cc-num = <6>; 862 interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; 863 max-bit-width = <32>; 864 prescaler = <0>; 865 }; 866 867 timer133: timer@9b3000 { 868 compatible = "nordic,nrf-timer"; 869 reg = <0x9b3000 0x1000>; 870 status = "disabled"; 871 cc-num = <6>; 872 interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; 873 max-bit-width = <32>; 874 prescaler = <0>; 875 }; 876 877 pwm131: pwm@9b4000 { 878 compatible = "nordic,nrf-pwm"; 879 reg = <0x9b4000 0x1000>; 880 status = "disabled"; 881 interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; 882 #pwm-cells = <3>; 883 }; 884 885 i2c132: i2c@9b5000 { 886 compatible = "nordic,nrf-twim"; 887 reg = <0x9b5000 0x1000>; 888 status = "disabled"; 889 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 890 easydma-maxcnt-bits = <15>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 894 <NRF_FUN_TWIM_SCL>; 895 zephyr,pm-device-runtime-auto; 896 }; 897 898 spi132: spi@9b5000 { 899 compatible = "nordic,nrf-spim"; 900 reg = <0x9b5000 0x1000>; 901 status = "disabled"; 902 easydma-maxcnt-bits = <15>; 903 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 904 max-frequency = <DT_FREQ_M(8)>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 rx-delay-supported; 908 rx-delay = <1>; 909 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 910 <NRF_FUN_SPIM_SCK>, 911 <NRF_FUN_SPIS_MISO>, 912 <NRF_FUN_SPIS_SCK>; 913 }; 914 915 uart132: uart@9b5000 { 916 compatible = "nordic,nrf-uarte"; 917 reg = <0x9b5000 0x1000>; 918 status = "disabled"; 919 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 920 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 921 endtx-stoptx-supported; 922 frame-timeout-supported; 923 }; 924 925 i2c133: i2c@9b6000 { 926 compatible = "nordic,nrf-twim"; 927 reg = <0x9b6000 0x1000>; 928 status = "disabled"; 929 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 930 easydma-maxcnt-bits = <15>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 934 <NRF_FUN_TWIM_SCL>; 935 zephyr,pm-device-runtime-auto; 936 }; 937 938 spi133: spi@9b6000 { 939 compatible = "nordic,nrf-spim"; 940 reg = <0x9b6000 0x1000>; 941 status = "disabled"; 942 easydma-maxcnt-bits = <15>; 943 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 944 max-frequency = <DT_FREQ_M(8)>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 rx-delay-supported; 948 rx-delay = <1>; 949 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 950 <NRF_FUN_SPIM_SCK>, 951 <NRF_FUN_SPIS_MISO>, 952 <NRF_FUN_SPIS_SCK>; 953 }; 954 955 uart133: uart@9b6000 { 956 compatible = "nordic,nrf-uarte"; 957 reg = <0x9b6000 0x1000>; 958 status = "disabled"; 959 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 960 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 961 endtx-stoptx-supported; 962 frame-timeout-supported; 963 }; 964 965 dppic135: dppic@9c1000 { 966 compatible = "nordic,nrf-dppic-global"; 967 reg = <0x9c1000 0x1000>; 968 status = "disabled"; 969 }; 970 971 timer134: timer@9c2000 { 972 compatible = "nordic,nrf-timer"; 973 reg = <0x9c2000 0x1000>; 974 status = "disabled"; 975 cc-num = <6>; 976 interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; 977 max-bit-width = <32>; 978 prescaler = <0>; 979 }; 980 981 timer135: timer@9c3000 { 982 compatible = "nordic,nrf-timer"; 983 reg = <0x9c3000 0x1000>; 984 status = "disabled"; 985 cc-num = <6>; 986 interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; 987 max-bit-width = <32>; 988 prescaler = <0>; 989 }; 990 991 pwm132: pwm@9c4000 { 992 compatible = "nordic,nrf-pwm"; 993 reg = <0x9c4000 0x1000>; 994 status = "disabled"; 995 interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; 996 #pwm-cells = <3>; 997 }; 998 999 i2c134: i2c@9c5000 { 1000 compatible = "nordic,nrf-twim"; 1001 reg = <0x9c5000 0x1000>; 1002 status = "disabled"; 1003 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1004 easydma-maxcnt-bits = <15>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1008 <NRF_FUN_TWIM_SCL>; 1009 zephyr,pm-device-runtime-auto; 1010 }; 1011 1012 spi134: spi@9c5000 { 1013 compatible = "nordic,nrf-spim"; 1014 reg = <0x9c5000 0x1000>; 1015 status = "disabled"; 1016 easydma-maxcnt-bits = <15>; 1017 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1018 max-frequency = <DT_FREQ_M(8)>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 rx-delay-supported; 1022 rx-delay = <1>; 1023 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1024 <NRF_FUN_SPIM_SCK>, 1025 <NRF_FUN_SPIS_MISO>, 1026 <NRF_FUN_SPIS_SCK>; 1027 }; 1028 1029 uart134: uart@9c5000 { 1030 compatible = "nordic,nrf-uarte"; 1031 reg = <0x9c5000 0x1000>; 1032 status = "disabled"; 1033 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1034 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1035 endtx-stoptx-supported; 1036 frame-timeout-supported; 1037 }; 1038 1039 i2c135: i2c@9c6000 { 1040 compatible = "nordic,nrf-twim"; 1041 reg = <0x9c6000 0x1000>; 1042 status = "disabled"; 1043 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1044 easydma-maxcnt-bits = <15>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1048 <NRF_FUN_TWIM_SCL>; 1049 zephyr,pm-device-runtime-auto; 1050 }; 1051 1052 spi135: spi@9c6000 { 1053 compatible = "nordic,nrf-spim"; 1054 reg = <0x9c6000 0x1000>; 1055 status = "disabled"; 1056 easydma-maxcnt-bits = <15>; 1057 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1058 max-frequency = <DT_FREQ_M(8)>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 rx-delay-supported; 1062 rx-delay = <1>; 1063 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1064 <NRF_FUN_SPIM_SCK>, 1065 <NRF_FUN_SPIS_MISO>, 1066 <NRF_FUN_SPIS_SCK>; 1067 }; 1068 1069 uart135: uart@9c6000 { 1070 compatible = "nordic,nrf-uarte"; 1071 reg = <0x9c6000 0x1000>; 1072 status = "disabled"; 1073 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1074 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1075 endtx-stoptx-supported; 1076 frame-timeout-supported; 1077 }; 1078 1079 dppic136: dppic@9d1000 { 1080 compatible = "nordic,nrf-dppic-global"; 1081 reg = <0x9d1000 0x1000>; 1082 status = "disabled"; 1083 }; 1084 1085 timer136: timer@9d2000 { 1086 compatible = "nordic,nrf-timer"; 1087 reg = <0x9d2000 0x1000>; 1088 status = "disabled"; 1089 cc-num = <6>; 1090 interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; 1091 max-bit-width = <32>; 1092 prescaler = <0>; 1093 }; 1094 1095 timer137: timer@9d3000 { 1096 compatible = "nordic,nrf-timer"; 1097 reg = <0x9d3000 0x1000>; 1098 status = "disabled"; 1099 cc-num = <6>; 1100 interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; 1101 max-bit-width = <32>; 1102 prescaler = <0>; 1103 }; 1104 1105 pwm133: pwm@9d4000 { 1106 compatible = "nordic,nrf-pwm"; 1107 reg = <0x9d4000 0x1000>; 1108 status = "disabled"; 1109 interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; 1110 #pwm-cells = <3>; 1111 }; 1112 1113 i2c136: i2c@9d5000 { 1114 compatible = "nordic,nrf-twim"; 1115 reg = <0x9d5000 0x1000>; 1116 status = "disabled"; 1117 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1118 easydma-maxcnt-bits = <15>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1122 <NRF_FUN_TWIM_SCL>; 1123 zephyr,pm-device-runtime-auto; 1124 }; 1125 1126 spi136: spi@9d5000 { 1127 compatible = "nordic,nrf-spim"; 1128 reg = <0x9d5000 0x1000>; 1129 status = "disabled"; 1130 easydma-maxcnt-bits = <15>; 1131 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1132 max-frequency = <DT_FREQ_M(8)>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 rx-delay-supported; 1136 rx-delay = <1>; 1137 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1138 <NRF_FUN_SPIM_SCK>, 1139 <NRF_FUN_SPIS_MISO>, 1140 <NRF_FUN_SPIS_SCK>; 1141 }; 1142 1143 uart136: uart@9d5000 { 1144 compatible = "nordic,nrf-uarte"; 1145 reg = <0x9d5000 0x1000>; 1146 status = "disabled"; 1147 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1148 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1149 endtx-stoptx-supported; 1150 frame-timeout-supported; 1151 }; 1152 1153 i2c137: i2c@9d6000 { 1154 compatible = "nordic,nrf-twim"; 1155 reg = <0x9d6000 0x1000>; 1156 status = "disabled"; 1157 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1158 easydma-maxcnt-bits = <15>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1162 <NRF_FUN_TWIM_SCL>; 1163 zephyr,pm-device-runtime-auto; 1164 }; 1165 1166 spi137: spi@9d6000 { 1167 compatible = "nordic,nrf-spim"; 1168 reg = <0x9d6000 0x1000>; 1169 status = "disabled"; 1170 easydma-maxcnt-bits = <15>; 1171 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1172 max-frequency = <DT_FREQ_M(8)>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 rx-delay-supported; 1176 rx-delay = <1>; 1177 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1178 <NRF_FUN_SPIM_SCK>, 1179 <NRF_FUN_SPIS_MISO>, 1180 <NRF_FUN_SPIS_SCK>; 1181 }; 1182 1183 uart137: uart@9d6000 { 1184 compatible = "nordic,nrf-uarte"; 1185 reg = <0x9d6000 0x1000>; 1186 status = "disabled"; 1187 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1188 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1189 endtx-stoptx-supported; 1190 frame-timeout-supported; 1191 }; 1192 }; 1193 }; 1194 1195 cpuapp_ppb: cpuapp-ppb-bus { 1196 #address-cells = <1>; 1197 #size-cells = <1>; 1198 1199 cpuapp_systick: timer@e000e010 { 1200 compatible = "arm,armv8m-systick"; 1201 reg = <0xe000e010 0x10>; 1202 status = "disabled"; 1203 }; 1204 1205 cpuapp_nvic: interrupt-controller@e000e100 { 1206 compatible = "arm,v8m-nvic"; 1207 reg = <0xe000e100 0xc00>; 1208 arm,num-irq-priority-bits = <3>; 1209 #interrupt-cells = <2>; 1210 interrupt-controller; 1211 #address-cells = <1>; 1212 }; 1213 }; 1214 1215 cpurad_ppb: cpurad-ppb-bus { 1216 #address-cells = <1>; 1217 #size-cells = <1>; 1218 1219 cpurad_systick: timer@e000e010 { 1220 compatible = "arm,armv8m-systick"; 1221 reg = <0xe000e010 0x10>; 1222 status = "disabled"; 1223 }; 1224 1225 cpurad_nvic: interrupt-controller@e000e100 { 1226 compatible = "arm,v8m-nvic"; 1227 reg = <0xe000e100 0xc00>; 1228 arm,num-irq-priority-bits = <3>; 1229 #interrupt-cells = <2>; 1230 interrupt-controller; 1231 #address-cells = <1>; 1232 }; 1233 }; 1234 1235 cpuppr_private: cpuppr-private-bus { 1236 #address-cells = <1>; 1237 #size-cells = <1>; 1238 1239 cpuppr_clic: interrupt-controller@5f909000 { 1240 compatible = "nordic,nrf-clic"; 1241 reg = <0x5f909000 0x3000>; 1242 status = "disabled"; 1243 #interrupt-cells = <2>; 1244 interrupt-controller; 1245 #address-cells = <1>; 1246 }; 1247 }; 1248 1249 temp_nrfs: temp { 1250 compatible = "nordic,nrf-temp-nrfs"; 1251 status = "disabled"; 1252 }; 1253}; 1254
