1/* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/pwm/pwm.h> 12#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 13#include <zephyr/dt-bindings/reset/stm32h7rs_reset.h> 14#include <zephyr/dt-bindings/adc/stm32h7_adc.h> 15#include <zephyr/dt-bindings/adc/adc.h> 16#include <zephyr/dt-bindings/memory-attr/memory-attr.h> 17#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 18#include <freq.h> 19 20/* 21 * STM32H7RS line contains has many common peripherals with STM32H7. 22 */ 23 24/ { 25 chosen { 26 zephyr,entropy = &rng; 27 zephyr,flash-controller = &flash; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-m7"; 37 reg = <0>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 41 mpu: mpu@e000ed90 { 42 compatible = "arm,armv7m-mpu"; 43 reg = <0xe000ed90 0x40>; 44 }; 45 }; 46 }; 47 48 /* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */ 49 sram0: memory@24000000 { 50 compatible = "mmio-sram"; 51 reg = <0x24000000 DT_SIZE_K(128)>; 52 }; 53 54 /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ 55 sram1: memory@30000000 { 56 reg = <0x30000000 DT_SIZE_K(16)>; 57 compatible = "zephyr,memory-region", "mmio-sram"; 58 zephyr,memory-region = "SRAM1"; 59 }; 60 61 /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ 62 sram2: memory@30004000 { 63 compatible = "zephyr,memory-region", "mmio-sram"; 64 reg = <0x30004000 DT_SIZE_K(16)>; 65 zephyr,memory-region = "SRAM2"; 66 }; 67 68 dtcm: memory@20000000 { 69 compatible = "zephyr,memory-region", "arm,dtcm"; 70 reg = <0x20000000 DT_SIZE_K(128)>; 71 zephyr,memory-region = "DTCM"; 72 }; 73 74 itcm: memory@0 { 75 compatible = "zephyr,memory-region", "arm,itcm"; 76 reg = <0x00000000 DT_SIZE_K(64)>; 77 zephyr,memory-region = "ITCM"; 78 }; 79 80 ext_memory: memory@70000000 { 81 compatible = "zephyr,memory-region"; 82 reg = <0x70000000 DT_SIZE_M(256)>; 83 zephyr,memory-region = "EXTMEM"; 84 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; 85 }; 86 87 clocks { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 clk_hse: clk-hse { 92 #clock-cells = <0>; 93 compatible = "st,stm32-hse-clock"; 94 status = "disabled"; 95 }; 96 97 clk_hsi: clk-hsi { 98 #clock-cells = <0>; 99 compatible = "st,stm32h7-hsi-clock"; 100 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ 101 clock-frequency = <DT_FREQ_M(64)>; 102 status = "disabled"; 103 }; 104 105 clk_hsi48: clk-hsi48 { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <DT_FREQ_M(48)>; 109 status = "disabled"; 110 }; 111 112 clk_csi: clk-csi { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <DT_FREQ_M(4)>; 116 status = "disabled"; 117 }; 118 119 clk_lse: clk-lse { 120 #clock-cells = <0>; 121 compatible = "st,stm32-lse-clock"; 122 clock-frequency = <32768>; 123 driving-capability = <0>; 124 status = "disabled"; 125 }; 126 127 clk_lsi: clk-lsi { 128 #clock-cells = <0>; 129 compatible = "fixed-clock"; 130 clock-frequency = <DT_FREQ_K(32)>; 131 status = "disabled"; 132 }; 133 134 pll: pll@0 { 135 #clock-cells = <0>; 136 compatible = "st,stm32h7rs-pll-clock"; 137 reg = <0>; 138 status = "disabled"; 139 }; 140 141 pll2: pll@1 { 142 #clock-cells = <0>; 143 compatible = "st,stm32h7rs-pll-clock"; 144 reg = <1>; 145 status = "disabled"; 146 }; 147 148 pll3: pll@2 { 149 #clock-cells = <0>; 150 compatible = "st,stm32h7rs-pll-clock"; 151 reg = <2>; 152 status = "disabled"; 153 }; 154 155 perck: perck { 156 #clock-cells = <0>; 157 compatible = "st,stm32-clock-mux"; 158 status = "disabled"; 159 }; 160 }; 161 162 mcos { 163 mco1: mco1 { 164 compatible = "st,stm32-clock-mco"; 165 status = "disabled"; 166 }; 167 168 mco2: mco2 { 169 compatible = "st,stm32-clock-mco"; 170 status = "disabled"; 171 }; 172 }; 173 174 soc { 175 flash: flash-controller@52002000 { 176 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; 177 reg = <0x52002000 0x400>; 178 interrupts = <8 0>; 179 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; 180 181 #address-cells = <1>; 182 #size-cells = <1>; 183 184 flash0: flash@8000000 { 185 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 186 write-block-size = <32>; 187 erase-block-size = <DT_SIZE_K(8)>; 188 /* maximum erase time for a 8K sector */ 189 max-erase-time = <3>; 190 }; 191 }; 192 193 rcc: rcc@58024400 { 194 compatible = "st,stm32h7rs-rcc"; 195 #clock-cells = <2>; 196 reg = <0x58024400 0x400>; 197 198 rctl: reset-controller { 199 compatible = "st,stm32-rcc-rctl"; 200 #reset-cells = <1>; 201 }; 202 }; 203 204 exti: interrupt-controller@58000000 { 205 compatible = "st,stm32h7rs-exti", "st,stm32-exti"; 206 interrupt-controller; 207 #interrupt-cells = <1>; 208 #address-cells = <1>; 209 reg = <0x58000000 0x400>; 210 /* SBS for interrupt */ 211 num-lines = <16>; 212 interrupts = <16 0>, <17 0>, <18 0>, <19 0>, 213 <20 0>, <21 0>, <22 0>, <23 0>, 214 <24 0>, <25 0>, <26 0>, <27 0>, 215 <28 0>, <29 0>, <30 0>, <31 0>; 216 interrupt-names = "line0", "line1", "line2", "line3", 217 "line4", "line5", "line6", "line7", 218 "line8", "line9", "line10", "line11", 219 "line12", "line13", "line14", "line15"; 220 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 221 <4 1>, <5 1>, <6 1>, <7 1>, 222 <8 1>, <9 1>, <10 1>, <11 1>, 223 <12 1>, <13 1>, <14 1>, <15 1>; 224 }; 225 226 pinctrl: pin-controller@58020000 { 227 compatible = "st,stm32-pinctrl"; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 reg = <0x58020000 0x2400>; 231 232 gpioa: gpio@58020000 { 233 compatible = "st,stm32-gpio"; 234 gpio-controller; 235 #gpio-cells = <2>; 236 reg = <0x58020000 0x400>; 237 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>; 238 }; 239 240 gpiob: gpio@58020400 { 241 compatible = "st,stm32-gpio"; 242 gpio-controller; 243 #gpio-cells = <2>; 244 reg = <0x58020400 0x400>; 245 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>; 246 }; 247 248 gpioc: gpio@58020800 { 249 compatible = "st,stm32-gpio"; 250 gpio-controller; 251 #gpio-cells = <2>; 252 reg = <0x58020800 0x400>; 253 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>; 254 }; 255 256 gpiod: gpio@58020C00 { 257 compatible = "st,stm32-gpio"; 258 gpio-controller; 259 #gpio-cells = <2>; 260 reg = <0x58020C00 0x400>; 261 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>; 262 }; 263 264 gpioe: gpio@58021000 { 265 compatible = "st,stm32-gpio"; 266 gpio-controller; 267 #gpio-cells = <2>; 268 reg = <0x58021000 0x400>; 269 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>; 270 }; 271 272 gpiof: gpio@58021400 { 273 compatible = "st,stm32-gpio"; 274 gpio-controller; 275 #gpio-cells = <2>; 276 reg = <0x58021400 0x400>; 277 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>; 278 }; 279 280 gpiog: gpio@58021800 { 281 compatible = "st,stm32-gpio"; 282 gpio-controller; 283 #gpio-cells = <2>; 284 reg = <0x58021800 0x400>; 285 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>; 286 }; 287 288 gpioh: gpio@58021c00 { 289 compatible = "st,stm32-gpio"; 290 gpio-controller; 291 #gpio-cells = <2>; 292 reg = <0x58021c00 0x400>; 293 clocks = <&rcc STM32_CLOCK(AHB4, 7U)>; 294 }; 295 296 gpiom: gpio@58023000 { 297 compatible = "st,stm32-gpio"; 298 gpio-controller; 299 #gpio-cells = <2>; 300 reg = <0x58023000 0x400>; 301 clocks = <&rcc STM32_CLOCK(AHB4, 12U)>; 302 }; 303 304 gpion: gpio@58023400 { 305 compatible = "st,stm32-gpio"; 306 gpio-controller; 307 #gpio-cells = <2>; 308 reg = <0x58023400 0x400>; 309 clocks = <&rcc STM32_CLOCK(AHB4, 13U)>; 310 }; 311 312 gpioo: gpio@58023800 { 313 compatible = "st,stm32-gpio"; 314 gpio-controller; 315 #gpio-cells = <2>; 316 reg = <0x58023800 0x400>; 317 clocks = <&rcc STM32_CLOCK(AHB4, 14U)>; 318 }; 319 320 gpiop: gpio@58023c00 { 321 compatible = "st,stm32-gpio"; 322 gpio-controller; 323 #gpio-cells = <2>; 324 reg = <0x58023c00 0x400>; 325 clocks = <&rcc STM32_CLOCK(AHB4, 15U)>; 326 }; 327 }; 328 329 usart1: serial@42001000 { 330 compatible = "st,stm32-usart", "st,stm32-uart"; 331 reg = <0x42001000 0x400>; 332 clocks = <&rcc STM32_CLOCK(APB2, 4U)>; 333 resets = <&rctl STM32_RESET(APB2, 4U)>; 334 interrupts = <82 0>; 335 status = "disabled"; 336 }; 337 usart2: serial@40004400 { 338 compatible = "st,stm32-usart", "st,stm32-uart"; 339 reg = <0x40004400 0x400>; 340 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 341 resets = <&rctl STM32_RESET(APB1L, 17U)>; 342 interrupts = <83 0>; 343 status = "disabled"; 344 }; 345 usart3: serial@40004800 { 346 compatible = "st,stm32-usart", "st,stm32-uart"; 347 reg = <0x40004800 0x400>; 348 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 349 resets = <&rctl STM32_RESET(APB1L, 18U)>; 350 interrupts = <84 0>; 351 status = "disabled"; 352 }; 353 uart4: serial@40004c00 { 354 compatible ="st,stm32-uart"; 355 reg = <0x40004c00 0x400>; 356 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 357 resets = <&rctl STM32_RESET(APB1L, 19U)>; 358 interrupts = <85 0>; 359 status = "disabled"; 360 }; 361 uart5: serial@40005000 { 362 compatible = "st,stm32-uart"; 363 reg = <0x40005000 0x400>; 364 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 365 resets = <&rctl STM32_RESET(APB1L, 20U)>; 366 interrupts = <86 0>; 367 status = "disabled"; 368 }; 369 uart7: serial@40007800 { 370 compatible = "st,stm32-uart"; 371 reg = <0x40007800 0x400>; 372 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 373 resets = <&rctl STM32_RESET(APB1L, 30U)>; 374 interrupts = <87 0>; 375 status = "disabled"; 376 }; 377 uart8: serial@40007c00 { 378 compatible = "st,stm32-uart"; 379 reg = <0x40007c00 0x400>; 380 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 381 resets = <&rctl STM32_RESET(APB1L, 31U)>; 382 interrupts = <88 0>; 383 status = "disabled"; 384 }; 385 386 lpuart1: serial@58000c00 { 387 compatible = "st,stm32-lpuart", "st,stm32-uart"; 388 reg = <0x58000c00 0x400>; 389 clocks = <&rcc STM32_CLOCK(APB4, 3U)>; 390 resets = <&rctl STM32_RESET(APB4, 3U)>; 391 interrupts = <131 0>; 392 status = "disabled"; 393 }; 394 395 i2c1: i2c@40005400 { 396 compatible = "st,stm32-i2c-v2"; 397 clock-frequency = <I2C_BITRATE_STANDARD>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <0x40005400 0x400>; 401 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 402 interrupts = <76 0>, <77 0>; 403 interrupt-names = "event", "error"; 404 status = "disabled"; 405 }; 406 407 i2c2: i2c@40005800 { 408 compatible = "st,stm32-i2c-v2"; 409 clock-frequency = <I2C_BITRATE_STANDARD>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 reg = <0x40005800 0x400>; 413 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 414 interrupts = <78 0>, <79 0>; 415 interrupt-names = "event", "error"; 416 status = "disabled"; 417 }; 418 419 i2c3: i2c@40005c00 { 420 compatible = "st,stm32-i2c-v2"; 421 clock-frequency = <I2C_BITRATE_STANDARD>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 reg = <0x40005c00 0x400>; 425 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 426 interrupts = <80 0>, <81 0>; 427 interrupt-names = "event", "error"; 428 status = "disabled"; 429 }; 430 431 spi1: spi@42003000 { 432 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 reg = <0x42003000 0x400>; 436 clocks = <&rcc STM32_CLOCK(APB2, 12U)>, 437 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 438 interrupts = <58 0>; 439 status = "disabled"; 440 }; 441 442 spi2: spi@40003800 { 443 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 reg = <0x40003800 0x400>; 447 clocks = <&rcc STM32_CLOCK(APB1, 14U)>, 448 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; 449 interrupts = <59 0>; 450 status = "disabled"; 451 }; 452 453 spi3: spi@40003c00 { 454 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <0x40003c00 0x400>; 458 clocks = <&rcc STM32_CLOCK(APB1, 15U)>, 459 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; 460 interrupts = <60 0>; 461 status = "disabled"; 462 }; 463 464 spi4: spi@42003400 { 465 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 reg = <0x42003400 0x400>; 469 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 470 interrupts = <61 0>; 471 status = "disabled"; 472 }; 473 474 spi5: spi@42005000 { 475 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <0x42005000 0x400>; 479 clocks = <&rcc STM32_CLOCK(APB2, 20U)>; 480 interrupts = <62 0>; 481 status = "disabled"; 482 }; 483 484 i2s1: i2s@40013000 { 485 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 reg = <0x40013000 0x400>; 489 clocks = <&rcc STM32_CLOCK(APB2, 12U)>, 490 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 491 interrupts = <35 3>; 492 status = "disabled"; 493 }; 494 495 iwdg: iwdg1: watchdog@58004800 { 496 compatible = "st,stm32-watchdog"; 497 reg = <0x58004800 0x400>; 498 interrupts = <3 0>; 499 status = "disabled"; 500 }; 501 502 wwdg: wwdg1: watchdog@40002c00 { 503 compatible = "st,stm32-window-watchdog"; 504 reg = <0x40002c00 0x1000>; 505 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 506 interrupts = <4 7>; 507 status = "disabled"; 508 }; 509 510 timers1: timers@42000000 { 511 compatible = "st,stm32-timers"; 512 reg = <0x42000000 0x400>; 513 clocks = <&rcc STM32_CLOCK(APB2, 0U)>; 514 resets = <&rctl STM32_RESET(APB2, 0U)>; 515 interrupts = <47 0>, <48 0>, <49 0>, <50 0>; 516 interrupt-names = "brk", "up", "trgcom", "cc"; 517 st,prescaler = <0>; 518 status = "disabled"; 519 520 pwm { 521 compatible = "st,stm32-pwm"; 522 status = "disabled"; 523 #pwm-cells = <3>; 524 }; 525 }; 526 527 timers2: timers@40000000 { 528 compatible = "st,stm32-timers"; 529 reg = <0x40000000 0x400>; 530 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 531 resets = <&rctl STM32_RESET(APB1L, 0U)>; 532 interrupts = <51 0>; 533 interrupt-names = "global"; 534 st,prescaler = <0>; 535 status = "disabled"; 536 537 pwm { 538 compatible = "st,stm32-pwm"; 539 status = "disabled"; 540 #pwm-cells = <3>; 541 }; 542 543 counter { 544 compatible = "st,stm32-counter"; 545 status = "disabled"; 546 }; 547 }; 548 549 timers3: timers@40000400 { 550 compatible = "st,stm32-timers"; 551 reg = <0x40000400 0x400>; 552 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 553 resets = <&rctl STM32_RESET(APB1L, 1U)>; 554 interrupts = <52 0>; 555 interrupt-names = "global"; 556 st,prescaler = <0>; 557 status = "disabled"; 558 559 pwm { 560 compatible = "st,stm32-pwm"; 561 status = "disabled"; 562 #pwm-cells = <3>; 563 }; 564 565 counter { 566 compatible = "st,stm32-counter"; 567 status = "disabled"; 568 }; 569 }; 570 571 timers4: timers@40000800 { 572 compatible = "st,stm32-timers"; 573 reg = <0x40000800 0x400>; 574 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 575 resets = <&rctl STM32_RESET(APB1L, 2U)>; 576 interrupts = <53 0>; 577 interrupt-names = "global"; 578 st,prescaler = <0>; 579 status = "disabled"; 580 581 pwm { 582 compatible = "st,stm32-pwm"; 583 status = "disabled"; 584 #pwm-cells = <3>; 585 }; 586 587 counter { 588 compatible = "st,stm32-counter"; 589 status = "disabled"; 590 }; 591 }; 592 593 timers5: timers@40000c00 { 594 compatible = "st,stm32-timers"; 595 reg = <0x40000c00 0x400>; 596 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 597 resets = <&rctl STM32_RESET(APB1L, 3U)>; 598 interrupts = <54 0>; 599 interrupt-names = "global"; 600 st,prescaler = <0>; 601 status = "disabled"; 602 603 pwm { 604 compatible = "st,stm32-pwm"; 605 status = "disabled"; 606 #pwm-cells = <3>; 607 }; 608 609 counter { 610 compatible = "st,stm32-counter"; 611 status = "disabled"; 612 }; 613 }; 614 615 timers6: timers@40001000 { 616 compatible = "st,stm32-timers"; 617 reg = <0x40001000 0x400>; 618 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 619 resets = <&rctl STM32_RESET(APB1L, 4U)>; 620 interrupts = <55 0>; 621 interrupt-names = "global"; 622 st,prescaler = <0>; 623 status = "disabled"; 624 625 counter { 626 compatible = "st,stm32-counter"; 627 status = "disabled"; 628 }; 629 }; 630 631 timers7: timers@40001400 { 632 compatible = "st,stm32-timers"; 633 reg = <0x40001400 0x400>; 634 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 635 resets = <&rctl STM32_RESET(APB1L, 5U)>; 636 interrupts = <56 0>; 637 interrupt-names = "global"; 638 st,prescaler = <0>; 639 status = "disabled"; 640 641 counter { 642 compatible = "st,stm32-counter"; 643 status = "disabled"; 644 }; 645 }; 646 647 timers9: timers@42004c00 { 648 compatible = "st,stm32-timers"; 649 reg = <0x42004c00 0x400>; 650 clocks = <&rcc STM32_CLOCK(APB2, 19U)>; 651 resets = <&rctl STM32_RESET(APB2, 19U)>; 652 interrupts = <57 0>; 653 interrupt-names = "global"; 654 st,prescaler = <0>; 655 status = "disabled"; 656 657 counter { 658 compatible = "st,stm32-counter"; 659 status = "disabled"; 660 }; 661 }; 662 663 timers15: timers@42004000 { 664 compatible = "st,stm32-timers"; 665 reg = <0x42004000 0x400>; 666 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 667 resets = <&rctl STM32_RESET(APB2, 16U)>; 668 interrupts = <116 0>; 669 interrupt-names = "global"; 670 st,prescaler = <0>; 671 status = "disabled"; 672 673 pwm { 674 compatible = "st,stm32-pwm"; 675 status = "disabled"; 676 #pwm-cells = <3>; 677 }; 678 679 counter { 680 compatible = "st,stm32-counter"; 681 status = "disabled"; 682 }; 683 }; 684 685 timers16: timers@42004400 { 686 compatible = "st,stm32-timers"; 687 reg = <0x42004400 0x400>; 688 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 689 resets = <&rctl STM32_RESET(APB2, 17U)>; 690 interrupts = <117 0>; 691 interrupt-names = "global"; 692 st,prescaler = <0>; 693 status = "disabled"; 694 695 pwm { 696 compatible = "st,stm32-pwm"; 697 status = "disabled"; 698 #pwm-cells = <3>; 699 }; 700 701 counter { 702 compatible = "st,stm32-counter"; 703 status = "disabled"; 704 }; 705 }; 706 707 timers17: timers@42004800 { 708 compatible = "st,stm32-timers"; 709 reg = <0x42004800 0x400>; 710 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 711 resets = <&rctl STM32_RESET(APB2, 18U)>; 712 interrupts = <118 0>; 713 interrupt-names = "global"; 714 st,prescaler = <0>; 715 status = "disabled"; 716 717 pwm { 718 compatible = "st,stm32-pwm"; 719 status = "disabled"; 720 #pwm-cells = <3>; 721 }; 722 723 counter { 724 compatible = "st,stm32-counter"; 725 status = "disabled"; 726 }; 727 }; 728 729 lptim1: timers@40002400 { 730 compatible = "st,stm32-lptim"; 731 clocks = <&rcc STM32_CLOCK(APB1, 9U)>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 reg = <0x40002400 0x400>; 735 interrupts = <119 1>; 736 interrupt-names = "wakeup"; 737 status = "disabled"; 738 }; 739 740 adc1: adc@40022000 { 741 compatible = "st,stm32-adc"; 742 reg = <0x40022000 0x400>; 743 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 744 interrupts = <38 0>; 745 status = "disabled"; 746 #io-channel-cells = <1>; 747 resolutions = <STM32_ADC_RES(12, 0x00) 748 STM32_ADC_RES(10, 0x01) 749 STM32_ADC_RES(8, 0x2) 750 STM32_ADC_RES(6, 0x3)>; 751 sampling-times = <3 7 13 25 48 93 248 641>; 752 st,adc-sequencer = "FULLY_CONFIGURABLE"; 753 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 754 }; 755 756 adc2: adc@40022100 { 757 compatible = "st,stm32-adc"; 758 reg = <0x40022100 0x400>; 759 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 760 interrupts = <38 0>; 761 status = "disabled"; 762 #io-channel-cells = <1>; 763 resolutions = <STM32_ADC_RES(12, 0x00) 764 STM32_ADC_RES(10, 0x01) 765 STM32_ADC_RES(8, 0x02) 766 STM32_ADC_RES(6, 0x03)>; 767 sampling-times = <3 7 13 25 48 93 248 641>; 768 st,adc-sequencer = "FULLY_CONFIGURABLE"; 769 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 770 }; 771 772 rng: rng@48020000 { 773 compatible = "st,stm32-rng"; 774 reg = <0x48020000 0x400>; 775 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; 776 interrupts = <37 0>; 777 status = "disabled"; 778 }; 779 }; 780 781 die_temp: dietemp { 782 compatible = "st,stm32-temp-cal"; 783 ts-cal1-addr = <0x08FFF814>; 784 ts-cal2-addr = <0x08FFF818>; 785 ts-cal1-temp = <30>; 786 ts-cal2-temp = <130>; 787 ts-cal-vrefanalog = <3300>; 788 ts-cal-resolution = <12>; 789 io-channels = <&adc1 16>; 790 status = "disabled"; 791 }; 792 793 vbat: vbat { 794 compatible = "st,stm32-vbat"; 795 ratio = <4>; 796 status = "disabled"; 797 io-channels = <&adc2 16>; 798 }; 799 800 vref: vref { 801 compatible = "st,stm32-vref"; 802 vrefint-cal-addr = <0x08fff810>; 803 vrefint-cal-mv = <3300>; 804 status = "disabled"; 805 io-channels = <&adc1 17>; 806 }; 807}; 808 809&nvic { 810 arm,num-irq-priority-bits = <4>; 811}; 812
