1 /*
2 * Copyright (c) 2024 Linumiz
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/devicetree.h>
9 #include <zephyr/drivers/adc.h>
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/pm/device.h>
15 #include <zephyr/sys/byteorder.h>
16 #include <zephyr/sys/util.h>
17 #include <zephyr/sys/util_macro.h>
18 #include <zephyr/drivers/adc/ads131m02.h>
19
20 #define ADC_CONTEXT_USES_KERNEL_TIMER
21 #include "adc_context.h"
22
23 LOG_MODULE_REGISTER(ads131m02, CONFIG_ADC_LOG_LEVEL);
24
25 #define ADS131M02_DEVICE_ID 0x22
26
27 /* Device settings Registers */
28 #define ADS131M02_ID_REG 0x00
29 #define ADS131M02_STATUS_REG 0x01
30
31 /* Global settings Registers */
32 #define ADS131M02_MODE_REG 0x02
33 #define ADS131M02_CLOCK_REG 0x03
34 #define ADS131M02_GAIN_REG 0x04
35 #define ADS131M02_CFG_REG 0x06
36 #define ADS131M02_THRESH_MSB_REG 0x07
37 #define ADS131M02_THRESH_LSB_REG 0x08
38
39 /* Channel 0 settings Registers */
40 #define ADS131M02_CH0_CFG_REG 0x09
41 #define ADS131M02_CH0_OCAL_MSB_REG 0x0A
42 #define ADS131M02_CH0_OCAL_LSB_REG 0x0B
43 #define ADS131M02_CH0_GCAL_MSB_REG 0x0C
44 #define ADS131M02_CH0_GCAL_LSB_REG 0x0D
45
46 /* Channel 1 settings Registers */
47 #define ADS131M02_CH1_CFG_REG 0x0E
48 #define ADS131M02_CH1_OCAL_MSB_REG 0x0F
49 #define ADS131M02_CH1_OCAL_LSB_REG 0x10
50 #define ADS131M02_CH1_GCAL_MSB_REG 0x11
51 #define ADS131M02_CH1_GCAL_LSB_REG 0x12
52
53 /* Register Map CRC Registers */
54 #define ADS131M02_REGMAP_CRC_REG 0x3E
55
56 #define ADC_CHANNEL_0 0
57 #define ADC_CHANNEL_1 1
58 #define ADS131M02_REF_INTERNAL 1200
59 #define ADS131M02_RESOLUTION 24
60
61 /* ADS131M02 cmds */
62 #define ADS131M02_NULL_CMD 0x0000
63 #define ADS131M02_RESET_CMD 0x0011
64 #define ADS131M02_STANDBY_CMD 0x0022
65 #define ADS131M02_WAKEUP_CMD 0x0033
66 #define ADS131M02_LOCK_CMD 0x0555
67 #define ADS131M02_UNLOCK_CMD 0x0655
68 #define ADS131M02_RREG_CMD 0xA000
69 #define ADS131M02_WREG_CMD 0x6000
70
71 #define ADS131M02_RESET_RSP 0xFF22
72
73 #define ADS131M02_GAIN0_MASK GENMASK(2, 0)
74 #define ADS131M02_GAIN1_MASK GENMASK(6, 4)
75 #define ADS131M02_CHANNEL0_ENABLE BIT(8)
76 #define ADS131M02_CHANNEL1_ENABLE BIT(9)
77 #define ADS131M02_DRDY_CH0_MASK BIT(0)
78 #define ADS131M02_DRDY_CH1_MASK BIT(1)
79 #define ADS131M02_OSR_256_MASK BIT(2)
80 #define ADS131M02_OSR_512_MASK BIT(3)
81 #define ADS131M02_OSR_1024_MASK BIT(3) | BIT(2)
82 #define ADS131M02_OSR_2048_MASK BIT(4)
83 #define ADS131M02_OSR_4096_MASK BIT(4) | BIT(2)
84 #define ADS131M02_OSR_8192_MASK BIT(4) | BIT(3)
85 #define ADS131M02_OSR_16384_MASK BIT(4) | BIT(3) | BIT(2)
86 #define ADS131M02_GC_MODE_MASK BIT(8)
87 #define ADS131M02_GC_DELAY_MASK GENMASK(12, 9)
88 #define ADS131M02_PWR_HR BIT(1) | BIT(0)
89 #define ADS131M02_PWR_LP BIT(0)
90
91 #define ADS131M02_DISABLE_ADC 0x000E
92 #define ADS131M02_RESET_DELAY 100
93
94 #define ADS131M02_GAIN_1 0
95 #define ADS131M02_GAIN_2 1
96 #define ADS131M02_GAIN_4 2
97 #define ADS131M02_GAIN_8 3
98 #define ADS131M02_GAIN_16 4
99 #define ADS131M02_GAIN_32 5
100 #define ADS131M02_GAIN_64 6
101 #define ADS131M02_GAIN_128 7
102
103 #define ADS131M02_GET_GAIN(channel_id, gain) \
104 FIELD_PREP(channel_id == 0 ? ADS131M02_GAIN0_MASK : \
105 ADS131M02_GAIN1_MASK, gain)
106
107 enum ads131m02_data_rate {
108 /* SPS */
109 ADS131M02_DR_250,
110 ADS131M02_DR_500,
111 ADS131M02_DR_1k,
112 ADS131M02_DR_2k,
113 ADS131M02_DR_4k,
114 ADS131M02_DR_8k,
115 ADS131M02_DR_16k,
116 ADS131M02_DR_32k,
117 };
118
119 struct ads131m02_config {
120 const struct spi_dt_spec spi;
121 const struct gpio_dt_spec gpio_drdy;
122 };
123
124 struct ads131m02_data {
125 struct adc_context ctx;
126 struct k_sem acq_sem;
127 struct k_sem drdy_sem;
128 struct gpio_callback callback_drdy;
129 int32_t *buffer;
130 int32_t *buffer_ptr;
131 };
132
ads131m02_transceive(const struct device * dev,uint8_t * send_buf,size_t send_buf_len,uint8_t * recv_buf,size_t recv_buf_len)133 static inline int ads131m02_transceive(const struct device *dev,
134 uint8_t *send_buf, size_t send_buf_len,
135 uint8_t *recv_buf, size_t recv_buf_len)
136 {
137 int ret;
138 const struct ads131m02_config *cfg = dev->config;
139
140 struct spi_buf tx_buf = {
141 .buf = send_buf,
142 .len = send_buf_len,
143 };
144 const struct spi_buf_set tx = {
145 .buffers = &tx_buf,
146 .count = 1
147 };
148
149 struct spi_buf rx_buf = {
150 .buf = recv_buf,
151 .len = recv_buf_len,
152 };
153 const struct spi_buf_set rx = {
154 .buffers = &rx_buf,
155 .count = 1,
156 };
157
158 ret = spi_transceive_dt(&cfg->spi, &tx, NULL);
159 if (ret != 0) {
160 return ret;
161 }
162
163 return spi_read_dt(&cfg->spi, &rx);
164 }
165
ads131m02_reg_read(const struct device * dev,uint16_t addr,uint8_t * read_buf,size_t read_buf_len)166 static int ads131m02_reg_read(const struct device *dev, uint16_t addr,
167 uint8_t *read_buf, size_t read_buf_len)
168 {
169 uint16_t temp;
170 uint8_t tx_buf[3] = {0};
171
172 temp = (uint16_t)(ADS131M02_RREG_CMD | (addr << 7));
173 sys_put_be16(temp, tx_buf);
174
175 return ads131m02_transceive(dev, tx_buf, sizeof(tx_buf),
176 read_buf, read_buf_len);
177 }
178
ads131m02_reg_write(const struct device * dev,uint16_t addr,uint16_t write_data)179 static int ads131m02_reg_write(const struct device *dev, uint16_t addr,
180 uint16_t write_data)
181 {
182 uint16_t temp;
183 uint8_t tx_buf[6] = {0};
184 uint8_t rx_buf[3] = {0};
185
186 temp = (uint16_t)(ADS131M02_WREG_CMD | (addr << 7));
187 sys_put_be16(temp, tx_buf);
188 sys_put_be16(write_data, &tx_buf[3]);
189
190 return ads131m02_transceive(dev, tx_buf, sizeof(tx_buf),
191 rx_buf, sizeof(rx_buf));
192
193 }
194
ads131m02_configure_gain(const struct device * dev,const struct adc_channel_cfg * channel_cfg)195 static inline int ads131m02_configure_gain(const struct device *dev,
196 const struct adc_channel_cfg *channel_cfg)
197 {
198 uint16_t gain_cfg;
199
200 switch (channel_cfg->gain) {
201 case ADC_GAIN_1:
202 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
203 ADS131M02_GAIN_1);
204 break;
205 case ADC_GAIN_2:
206 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
207 ADS131M02_GAIN_2);
208 break;
209 case ADC_GAIN_4:
210 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
211 ADS131M02_GAIN_4);
212 break;
213 case ADC_GAIN_8:
214 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
215 ADS131M02_GAIN_8);
216 break;
217 case ADC_GAIN_16:
218 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
219 ADS131M02_GAIN_16);
220 break;
221 case ADC_GAIN_32:
222 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
223 ADS131M02_GAIN_32);
224 break;
225 case ADC_GAIN_64:
226 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
227 ADS131M02_GAIN_64);
228 break;
229 case ADC_GAIN_128:
230 gain_cfg = ADS131M02_GET_GAIN(channel_cfg->channel_id,
231 ADS131M02_GAIN_128);
232 break;
233 default:
234 return -EINVAL;
235 }
236
237 return ads131m02_reg_write(dev, ADS131M02_GAIN_REG, gain_cfg);
238 }
239
ads131m02_acquistion_time(uint16_t acq_time,uint16_t * enable)240 static inline int ads131m02_acquistion_time(uint16_t acq_time, uint16_t *enable)
241 {
242 uint16_t acq_value = ADC_ACQ_TIME_VALUE(acq_time);
243
244 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
245 *enable |= ADS131M02_OSR_1024_MASK;
246 return 0;
247 }
248
249 if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
250 return -EINVAL;
251 }
252
253 if (acq_time == ADC_ACQ_TIME_MAX) {
254 *enable |= ADS131M02_OSR_16384_MASK;
255 return 0;
256 }
257
258 switch (acq_value) {
259 case ADS131M02_DR_250:
260 *enable |= ADS131M02_OSR_16384_MASK;
261 break;
262 case ADS131M02_DR_500:
263 *enable |= ADS131M02_OSR_8192_MASK;
264 break;
265 case ADS131M02_DR_1k:
266 *enable |= ADS131M02_OSR_4096_MASK;
267 break;
268 case ADS131M02_DR_2k:
269 *enable |= ADS131M02_OSR_2048_MASK;
270 break;
271 case ADS131M02_DR_4k:
272 *enable |= ADS131M02_OSR_1024_MASK;
273 break;
274 case ADS131M02_DR_8k:
275 *enable |= ADS131M02_OSR_512_MASK;
276 break;
277 case ADS131M02_DR_16k:
278 *enable |= ADS131M02_OSR_256_MASK;
279 break;
280 default:
281 return -EINVAL;
282 }
283
284 return 0;
285 }
286
ads131m02_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)287 static int ads131m02_setup(const struct device *dev,
288 const struct adc_channel_cfg *channel_cfg)
289 {
290 int ret;
291 uint16_t enable;
292 uint8_t read_data[3] = {0};
293
294 ret = ads131m02_reg_read(dev, ADS131M02_CLOCK_REG, read_data,
295 sizeof(read_data));
296 if (ret != 0) {
297 return ret;
298 }
299
300 enable = sys_get_be16(read_data);
301 switch (channel_cfg->channel_id) {
302 case ADC_CHANNEL_0:
303 enable |= ADS131M02_CHANNEL0_ENABLE;
304 break;
305 case ADC_CHANNEL_1:
306 enable |= ADS131M02_CHANNEL1_ENABLE;
307 break;
308 default:
309 return -EINVAL;
310 }
311
312 enable &= ~(ADS131M02_OSR_16384_MASK);
313 ret = ads131m02_acquistion_time(channel_cfg->acquisition_time, &enable);
314 if (ret < 0) {
315 return ret;
316 }
317
318 return ads131m02_reg_write(dev, ADS131M02_CLOCK_REG, enable);
319 }
320
ads131m02_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)321 static int ads131m02_channel_setup(const struct device *dev,
322 const struct adc_channel_cfg *channel_cfg)
323 {
324 int ret;
325
326 if (channel_cfg->channel_id != 0 && channel_cfg->channel_id != 1) {
327 return -EINVAL;
328 }
329
330 if (channel_cfg->reference != ADC_REF_INTERNAL) {
331 LOG_DBG("Unsupported Reference Voltage");
332 return -ENOTSUP;
333 }
334
335 if (!channel_cfg->differential) {
336 return -EINVAL;
337 }
338
339 ret = ads131m02_configure_gain(dev, channel_cfg);
340 if (ret != 0) {
341 return ret;
342 }
343
344 ret = ads131m02_setup(dev, channel_cfg);
345 if (ret != 0) {
346 return ret;
347 }
348
349 return 0;
350 }
351
ads131m02_validate_buffer_size(const struct adc_sequence * sequence)352 static int ads131m02_validate_buffer_size(const struct adc_sequence *sequence)
353 {
354 size_t needed = sizeof(int32_t);
355
356 if (sequence->options) {
357 needed *= (1 + sequence->options->extra_samplings);
358 }
359
360 if (sequence->buffer_size < needed) {
361 return -ENOMEM;
362 }
363
364 return 0;
365 }
366
ads131m02_validate_sequence(const struct adc_sequence * sequence)367 static int ads131m02_validate_sequence(const struct adc_sequence *sequence)
368 {
369 if (sequence->resolution != ADS131M02_RESOLUTION) {
370 return -EINVAL;
371 }
372
373 if (sequence->channels != BIT(0) && sequence->channels != BIT(1)) {
374 LOG_ERR("invalid channel");
375 return -EINVAL;
376 }
377
378 if (sequence->oversampling) {
379 return -EINVAL;
380 }
381
382 return ads131m02_validate_buffer_size(sequence);
383 }
384
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)385 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
386 bool repeat_sampling)
387 {
388 struct ads131m02_data *data = CONTAINER_OF(ctx, struct ads131m02_data, ctx);
389
390 if (repeat_sampling) {
391 data->buffer = data->buffer_ptr;
392 }
393 }
394
adc_context_start_sampling(struct adc_context * ctx)395 static void adc_context_start_sampling(struct adc_context *ctx)
396 {
397 struct ads131m02_data *data = CONTAINER_OF(ctx, struct ads131m02_data, ctx);
398
399 data->buffer_ptr = data->buffer;
400 k_sem_give(&data->acq_sem);
401 }
402
ads131m02_adc_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)403 static int ads131m02_adc_start_read(const struct device *dev,
404 const struct adc_sequence *sequence,
405 bool wait)
406 {
407 int ret;
408 struct ads131m02_data *data = dev->data;
409
410 ret = ads131m02_validate_sequence(sequence);
411 if (ret != 0) {
412 LOG_ERR("sequence validation failed");
413 return ret;
414 }
415
416 data->buffer = sequence->buffer;
417 adc_context_start_read(&data->ctx, sequence);
418 if (wait) {
419 ret = adc_context_wait_for_completion(&data->ctx);
420 }
421
422 return ret;
423 }
424
ads131m02_wait_drdy(const struct device * dev)425 static int ads131m02_wait_drdy(const struct device *dev)
426 {
427 struct ads131m02_data *data = dev->data;
428
429 return k_sem_take(&data->drdy_sem,
430 ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT);
431 }
432
ads131m02_read_sample(const struct device * dev,uint32_t channels,uint32_t * buffer)433 static int ads131m02_read_sample(const struct device *dev,
434 uint32_t channels, uint32_t *buffer)
435 {
436 int ret;
437 uint16_t int_status;
438 uint8_t tx_buf[4] = {0};
439 uint8_t rx_buf[12] = {0};
440
441 ret = ads131m02_transceive(dev, tx_buf, sizeof(tx_buf),
442 rx_buf, sizeof(rx_buf));
443 if (ret != 0) {
444 return ret;
445 }
446
447 int_status = sys_get_be16(&rx_buf[0]);
448 if ((int_status & ADS131M02_DRDY_CH0_MASK) && (channels & BIT(0))) {
449 *buffer = sys_get_be24(&rx_buf[3]);
450 } else if ((int_status & ADS131M02_DRDY_CH1_MASK) &&
451 (channels & BIT(1))) {
452 *buffer = sys_get_be24(&rx_buf[6]);
453 } else {
454 LOG_INF("No ADC Data Available");
455 }
456
457 return 0;
458 }
459
ads131m02_perform_read(const struct device * dev,const struct adc_sequence * sequence)460 static int ads131m02_perform_read(const struct device *dev,
461 const struct adc_sequence *sequence)
462 {
463 int ret;
464 struct ads131m02_data *data = dev->data;
465
466 k_sem_take(&data->acq_sem, K_FOREVER);
467 k_sem_reset(&data->drdy_sem);
468
469 ret = ads131m02_wait_drdy(dev);
470 if (ret != 0) {
471 goto error;
472 }
473
474 ret = ads131m02_read_sample(dev, sequence->channels, data->buffer);
475 if (ret != 0) {
476 goto error;
477 }
478
479 data->buffer++;
480 adc_context_on_sampling_done(&data->ctx, dev);
481
482 return 0;
483 error:
484 adc_context_complete(&data->ctx, ret);
485 return ret;
486 }
487
ads131m02_read(const struct device * dev,const struct adc_sequence * seq)488 static int ads131m02_read(const struct device *dev,
489 const struct adc_sequence *seq)
490 {
491 int ret;
492 struct ads131m02_data *data = dev->data;
493
494 adc_context_lock(&data->ctx, false, NULL);
495 ret = ads131m02_adc_start_read(dev, seq, false);
496
497 while (ret == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
498 ret = ads131m02_perform_read(dev, seq);
499 }
500
501 adc_context_release(&data->ctx, ret);
502
503 return ret;
504 }
505
ads131m02_data_ready_handler(const struct device * dev,struct gpio_callback * gpio_cb,uint32_t pins)506 static void ads131m02_data_ready_handler(const struct device *dev,
507 struct gpio_callback *gpio_cb,
508 uint32_t pins)
509 {
510 ARG_UNUSED(dev);
511 ARG_UNUSED(pins);
512
513 struct ads131m02_data *data = CONTAINER_OF(gpio_cb,
514 struct ads131m02_data, callback_drdy);
515
516 k_sem_give(&data->drdy_sem);
517 }
518
ads131m02_configure_gpio(const struct device * dev)519 static int ads131m02_configure_gpio(const struct device *dev)
520 {
521 int ret;
522 const struct ads131m02_config *cfg = dev->config;
523 struct ads131m02_data *data = dev->data;
524
525 ret = gpio_pin_configure_dt(&cfg->gpio_drdy, GPIO_INPUT);
526 if (ret != 0) {
527 return ret;
528 }
529
530 ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_drdy,
531 GPIO_INT_EDGE_TO_ACTIVE);
532 if (ret != 0) {
533 return ret;
534 }
535
536 gpio_init_callback(&data->callback_drdy, ads131m02_data_ready_handler,
537 BIT(cfg->gpio_drdy.pin));
538
539 return gpio_add_callback(cfg->gpio_drdy.port, &data->callback_drdy);
540 }
541
ads131m02_device_reset(const struct device * dev)542 static int ads131m02_device_reset(const struct device *dev)
543 {
544 int ret;
545 uint8_t tx_buf[12] = {0};
546 uint8_t rx_buf[3] = {0};
547
548 sys_put_be16(ADS131M02_RESET_CMD, tx_buf);
549 ret = ads131m02_transceive(dev, tx_buf, sizeof(tx_buf),
550 rx_buf, sizeof(rx_buf));
551
552 if (ret != 0) {
553 return ret;
554 }
555
556 if (sys_get_be16(rx_buf) != ADS131M02_RESET_RSP) {
557 return -EIO;
558 }
559
560 k_msleep(ADS131M02_RESET_DELAY);
561
562 return 0;
563 }
564
565 #if defined CONFIG_PM_DEVICE
ads131m02_pm(const struct device * dev,uint16_t cmd)566 static int ads131m02_pm(const struct device *dev, uint16_t cmd)
567 {
568 int ret;
569 uint8_t tx_buf[3] = {0};
570 uint8_t rx_buf[3] = {0};
571
572 sys_put_be16(cmd, tx_buf);
573 ret = ads131m02_transceive(dev, tx_buf, sizeof(tx_buf),
574 rx_buf, sizeof(rx_buf));
575 if (ret != 0) {
576 return ret;
577 }
578
579 if (rx_buf[1] != cmd) {
580 return -EIO;
581 }
582
583 return 0;
584 }
585
ads131m02_pm_action(const struct device * dev,enum pm_device_action action)586 static int ads131m02_pm_action(const struct device *dev,
587 enum pm_device_action action)
588 {
589 switch (action) {
590 case PM_DEVICE_ACTION_RESUME:
591 return ads131m02_pm(dev, ADS131M02_WAKEUP_CMD);
592 case PM_DEVICE_ACTION_SUSPEND:
593 return ads131m02_pm(dev, ADS131M02_STANDBY_CMD);
594 default:
595 return -EINVAL;
596 }
597 }
598 #endif /* CONFIG_PM_DEVICE */
599
ads131m02_set_adc_mode(const struct device * dev,enum ads131m02_adc_mode mode,enum ads131m02_gc_delay gc_delay)600 int ads131m02_set_adc_mode(const struct device *dev,
601 enum ads131m02_adc_mode mode,
602 enum ads131m02_gc_delay gc_delay)
603 {
604 uint16_t temp = 0;
605
606 switch (mode) {
607 case ADS131M02_CONTINUOUS_MODE:
608 break;
609 case ADS131M02_GLOBAL_CHOP_MODE:
610 temp |= ADS131M02_GC_MODE_MASK;
611 temp |= FIELD_PREP(ADS131M02_GC_DELAY_MASK, gc_delay);
612 break;
613 default:
614 return -EINVAL;
615 }
616
617 return ads131m02_reg_write(dev, ADS131M02_CFG_REG, temp);
618 }
619
ads131m02_set_power_mode(const struct device * dev,enum ads131m02_adc_power_mode mode)620 int ads131m02_set_power_mode(const struct device *dev,
621 enum ads131m02_adc_power_mode mode)
622 {
623 int ret;
624 uint16_t temp;
625 uint8_t buf[3] = {0};
626
627 ret = ads131m02_reg_read(dev, ADS131M02_CLOCK_REG, buf, sizeof(buf));
628 if (ret != 0) {
629 return ret;
630 }
631
632 temp = sys_get_be16(buf);
633 temp &= ~(ADS131M02_PWR_HR);
634
635 switch (mode) {
636 case ADS131M02_VLP:
637 break;
638 case ADS131M02_LP:
639 temp |= ADS131M02_PWR_LP;
640 break;
641 case ADS131M02_HR:
642 temp |= ADS131M02_PWR_HR;
643 break;
644 default:
645 return -EINVAL;
646 }
647
648 return ads131m02_reg_write(dev, ADS131M02_CLOCK_REG, temp);
649 }
650
651 static const struct adc_driver_api ads131m02_api = {
652 .channel_setup = ads131m02_channel_setup,
653 .read = ads131m02_read,
654 .ref_internal = ADS131M02_REF_INTERNAL,
655 };
656
ads131m02_init(const struct device * dev)657 static int ads131m02_init(const struct device *dev)
658 {
659 int ret;
660 uint8_t buf[3] = {0};
661 const struct ads131m02_config *cfg = dev->config;
662 struct ads131m02_data *data = dev->data;
663
664 if (!spi_is_ready_dt(&cfg->spi)) {
665 LOG_ERR("ADS131M02 is not ready");
666 return -ENODEV;
667 }
668
669 adc_context_init(&data->ctx);
670 k_sem_init(&data->acq_sem, 0, 1);
671 k_sem_init(&data->drdy_sem, 0, 1);
672
673 ret = ads131m02_configure_gpio(dev);
674 if (ret != 0) {
675 LOG_ERR("GPIO config failed %d", ret);
676 return ret;
677 }
678
679 ret = ads131m02_reg_read(dev, ADS131M02_ID_REG, buf, sizeof(buf));
680 if (ret != 0) {
681 return ret;
682 }
683
684 if (buf[0] != ADS131M02_DEVICE_ID) {
685 LOG_ERR("Device ID mismatch %d", buf[0]);
686 return -ENODEV;
687 }
688
689 ret = ads131m02_device_reset(dev);
690 if (ret != 0) {
691 LOG_WRN("Device is not reset");
692 }
693
694 /* By default, adc is configured, so disabling it */
695 ret = ads131m02_reg_write(dev, ADS131M02_CLOCK_REG,
696 ADS131M02_DISABLE_ADC);
697 if (ret != 0) {
698 return ret;
699 }
700
701 adc_context_unlock_unconditionally(&data->ctx);
702
703 #if defined CONFIG_PM_DEVICE
704 ret = ads131m02_pm(dev, ADS131M02_STANDBY_CMD);
705 if (ret != 0) {
706 return ret;
707 }
708
709 pm_device_init_suspended(dev);
710 #endif /* CONFIG_PM_DEVICE */
711
712 LOG_INF("ADS131M02 Initialised");
713
714 return 0;
715 }
716
717 #define DT_DRV_COMPAT ti_ads131m02
718
719 #define ADC_ADS131M02_INST_DEFINE(n) \
720 PM_DEVICE_DT_INST_DEFINE(n, ads131m02_pm_action); \
721 static const struct ads131m02_config config_##n = { \
722 .spi = SPI_DT_SPEC_INST_GET( \
723 n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | \
724 SPI_WORD_SET(8), 0), \
725 .gpio_drdy = GPIO_DT_SPEC_INST_GET(n, drdy_gpios), \
726 }; \
727 static struct ads131m02_data data_##n; \
728 DEVICE_DT_INST_DEFINE(n, ads131m02_init, \
729 PM_DEVICE_DT_INST_GET(n), \
730 &data_##n, &config_##n, POST_KERNEL, \
731 CONFIG_ADC_INIT_PRIORITY, &ads131m02_api);
732
733 DT_INST_FOREACH_STATUS_OKAY(ADC_ADS131M02_INST_DEFINE)
734
