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Searched defs:__CM4_REV (Results 1 – 25 of 272) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b100f128gm32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b100f128im32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b100f256gm32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b100f256im32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f128gm32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f128gm48.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f128im32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f256gm32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f256gm48.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f256im32.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defm32pg1b200f256im48.h184 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p131f256gm48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f256im48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f64gm32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f128gm32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f128gm48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f256gm32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f256im32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p131f64gm48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p132f128gm32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p132f128gm48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p132f256gm32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p132f256gm48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p132f64gm32.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro
Defr32fg1p132f64gm48.h198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ macro

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