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Searched defs:XCHAL_ICACHE_LINEWIDTH (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h159 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h241 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h241 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h241 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h214 #define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h241 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h234 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h214 #define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h239 #define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h293 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h293 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h286 #define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h281 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h293 #define XCHAL_ICACHE_LINEWIDTH 8 /* log2(I line size in bytes) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h291 #define XCHAL_ICACHE_LINEWIDTH 3 /* log2(I line size in bytes) */ macro