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Searched defs:XCHAL_HAVE_XEA1 (Results 1 – 9 of 9) sorted by relevance

/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h473 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h473 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h473 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h523 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h515 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h523 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h496 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h575 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h542 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ macro