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Searched defs:XCHAL_HAVE_AXI (Results 1 – 9 of 9) sorted by relevance

/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h277 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h277 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h277 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h249 #define XCHAL_HAVE_AXI 1 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h270 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h249 #define XCHAL_HAVE_AXI 1 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h277 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h355 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h319 #define XCHAL_HAVE_AXI 0 /* AXI bus */ macro