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Searched defs:XCHAL_DCACHE_LINESIZE (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h158 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h213 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h233 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h213 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h238 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h292 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h292 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h285 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h280 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h292 #define XCHAL_DCACHE_LINESIZE 256 /* D-cache line size in bytes */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h290 #define XCHAL_DCACHE_LINESIZE 8 /* D-cache line size in bytes */ macro