| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/ |
| D | MKE14Z4.h | 9617 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/ |
| D | MKE15Z4.h | 9619 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE12Z7/ |
| D | MKE12Z7.h | 12134 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/ |
| D | MKE16Z4.h | 10456 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE13Z7/ |
| D | MKE13Z7.h | 12137 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE17Z7/ |
| D | MKE17Z7.h | 12140 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/ |
| D | MKE14Z7.h | 12397 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/ |
| D | MKE15Z7.h | 12400 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/ |
| D | MKE16F16.h | 16316 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/ |
| D | MKE14F16.h | 15316 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/ |
| D | MKE18F16.h | 16322 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/ |
| D | K32L2A31A.h | 13913 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/ |
| D | K32L2A41A.h | 13913 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm0plus.h | 15132 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| D | K32L3A60_cm4.h | 15082 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 26000 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 25999 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ member
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