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Searched defs:MR (Results 1 – 25 of 131) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC802/
DLPC802.h1175 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC804/
DLPC804.h1557 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h5990 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h5999 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC844/
DLPC844.h1255 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC845/
DLPC845.h1661 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h8671 __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h1288 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h8673 __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h8509 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h1244 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
DLPC54114_cm4.h1255 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h9510 __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h1256 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h9406 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h9652 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2B11A/
DK32L2B11A.h10507 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2B31A/
DK32L2B31A.h10507 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2B21A/
DK32L2B21A.h10507 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h11370 __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h11373 __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h9248 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h5790 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h5790 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h10149 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member

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