Home
last modified time | relevance | path

Searched defs:LPSPI_CFGR1_PCSPOL_MASK (Results 1 – 25 of 60) sorted by relevance

123

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h385 #define LPSPI_CFGR1_PCSPOL_MASK (0xFF00U) /* Merged from fields with different po… macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h5221 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h5222 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h8249 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h5220 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h8251 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h8253 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7785 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7787 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h11432 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h10433 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h11437 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h9147 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h9147 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h10803 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
DK32L3A60_cm4.h11438 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h19884 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h13738 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h13737 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h22922 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h27085 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h27068 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h29619 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h28118 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h30825 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro

123