/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/ |
D | S32K344_LPSPI.h | 385 #define LPSPI_CFGR1_PCSPOL_MASK (0xFF00U) /* Merged from fields with different po… macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/ |
D | MKE14Z4.h | 5221 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/ |
D | MKE15Z4.h | 5222 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE12Z7/ |
D | MKE12Z7.h | 8249 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/ |
D | MKE16Z4.h | 5220 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE13Z7/ |
D | MKE13Z7.h | 8251 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE17Z7/ |
D | MKE17Z7.h | 8253 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/ |
D | MKE14Z7.h | 7785 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/ |
D | MKE15Z7.h | 7787 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/ |
D | MKE16F16.h | 11432 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/ |
D | MKE14F16.h | 10433 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/ |
D | MKE18F16.h | 11437 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/ |
D | K32L2A31A.h | 9147 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/ |
D | K32L2A41A.h | 9147 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/ |
D | K32L3A60_cm0plus.h | 10803 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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D | K32L3A60_cm4.h | 11438 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/ |
D | MIMXRT1011.h | 19884 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/ |
D | MCIMX7U5_cm4.h | 13738 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/ |
D | MCIMX7U3_cm4.h | 13737 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/ |
D | MIMXRT1015.h | 22922 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
D | MIMXRT1021.h | 27085 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
D | MIMXRT1024.h | 27068 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
D | MIMXRT1041.h | 29619 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
D | MIMXRT1051.h | 28118 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
D | MIMXRT1052.h | 30825 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
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