1 /* ns16550.c - NS16550D serial driver */
2
3 #define DT_DRV_COMPAT ns16550
4
5 /*
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2023 Intel Corp.
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 */
11
12 /**
13 * @brief NS16550 Serial Driver
14 *
15 * This is the driver for the Intel NS16550 UART Chip used on the PC 386.
16 * It uses the SCCs in asynchronous mode only.
17 *
18 * Before individual UART port can be used, uart_ns16550_port_init() has to be
19 * called to setup the port.
20 */
21
22 #include <errno.h>
23 #include <zephyr/kernel.h>
24 #include <zephyr/arch/cpu.h>
25 #include <zephyr/types.h>
26
27 #include <zephyr/init.h>
28 #include <zephyr/toolchain.h>
29 #include <zephyr/linker/sections.h>
30 #include <zephyr/drivers/uart.h>
31 #include <zephyr/drivers/clock_control.h>
32 #include <zephyr/pm/policy.h>
33 #include <zephyr/sys/sys_io.h>
34 #include <zephyr/spinlock.h>
35 #include <zephyr/irq.h>
36
37 #if defined(CONFIG_PINCTRL)
38 #include <zephyr/drivers/pinctrl.h>
39 #endif
40
41 #include <zephyr/drivers/serial/uart_ns16550.h>
42 #include <zephyr/logging/log.h>
43
44 LOG_MODULE_REGISTER(uart_ns16550, CONFIG_UART_LOG_LEVEL);
45
46 #define UART_NS16550_PCP_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(pcp)
47 #define UART_NS16550_DLF_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(dlf)
48 #define UART_NS16550_DMAS_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(dmas)
49
50 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
51 BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
52 #include <zephyr/drivers/pcie/pcie.h>
53 #endif
54
55 /* Is UART module 'resets' line property defined */
56 #define UART_NS16550_RESET_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
57
58 #if UART_NS16550_RESET_ENABLED
59 #include <zephyr/drivers/reset.h>
60 #endif
61
62 #if defined(CONFIG_UART_ASYNC_API)
63 #include <zephyr/drivers/dma.h>
64 #include <assert.h>
65
66 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
67 #include <zephyr/drivers/dma/dma_intel_lpss.h>
68 #endif
69
70 #endif
71
72 /* If any node has property io-mapped set, we need to support IO port
73 * access in the code and device config struct.
74 *
75 * Note that DT_ANY_INST_HAS_PROP_STATUS_OKAY() always returns true
76 * as io-mapped property is considered always exists and present,
77 * even if its value is zero. Therefore we cannot use it, and has to
78 * resort to the follow helper to see if any okay nodes have io-mapped
79 * as 1.
80 */
81 #define UART_NS16550_DT_PROP_IOMAPPED_HELPER(inst, prop, def) \
82 DT_INST_PROP_OR(inst, prop, def) ||
83
84 #define UART_NS16550_IOPORT_ENABLED \
85 (DT_INST_FOREACH_STATUS_OKAY_VARGS(UART_NS16550_DT_PROP_IOMAPPED_HELPER, io_mapped, 0) 0)
86
87 /* register definitions */
88
89 #define REG_THR 0x00 /* Transmitter holding reg. */
90 #define REG_RDR 0x00 /* Receiver data reg. */
91 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
92 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
93 #define REG_IER 0x01 /* Interrupt enable reg. */
94 #define REG_IIR 0x02 /* Interrupt ID reg. */
95 #define REG_FCR 0x02 /* FIFO control reg. */
96 #define REG_LCR 0x03 /* Line control reg. */
97 #define REG_MDC 0x04 /* Modem control reg. */
98 #define REG_LSR 0x05 /* Line status reg. */
99 #define REG_MSR 0x06 /* Modem status reg. */
100 #define REG_USR 0x7C /* UART status reg. (DW8250) */
101 #define REG_DLF 0xC0 /* Divisor Latch Fraction */
102 #define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
103 #define REG_MDR1 0x08 /* Mode control reg. (TI_K3) */
104
105 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
106 #define REG_LPSS_SRC_TRAN 0xAF8 /* SRC Transfer LPSS DMA */
107 #define REG_LPSS_CLR_SRC_TRAN 0xB48 /* Clear SRC Tran LPSS DMA */
108 #define REG_LPSS_MST 0xB20 /* Mask SRC Transfer LPSS DMA */
109 #endif
110
111 /* equates for interrupt enable register */
112
113 #define IER_RXRDY 0x01 /* receiver data ready */
114 #define IER_TBE 0x02 /* transmit bit enable */
115 #define IER_LSR 0x04 /* line status interrupts */
116 #define IER_MSI 0x08 /* modem status interrupts */
117
118 /* equates for interrupt identification register */
119
120 #define IIR_MSTAT 0x00 /* modem status interrupt */
121 #define IIR_NIP 0x01 /* no interrupt pending */
122 #define IIR_THRE 0x02 /* transmit holding register empty interrupt */
123 #define IIR_RBRF 0x04 /* receiver buffer register full interrupt */
124 #define IIR_LS 0x06 /* receiver line status interrupt */
125 #define IIR_MASK 0x07 /* interrupt id bits mask */
126 #define IIR_ID 0x06 /* interrupt ID mask without NIP */
127 #define IIR_BUSY 0x07 /* DesignWare APB busy detect */
128 #define IIR_FE 0xC0 /* FIFO mode enabled */
129 #define IIR_CH 0x0C /* Character timeout*/
130
131 /* equates for FIFO control register */
132
133 #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
134 #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
135 #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
136
137 /* equates for Apollo Lake clock control register (PRV_CLOCK_PARAMS) */
138
139 #define PCP_UPDATE 0x80000000 /* update clock */
140 #define PCP_EN 0x00000001 /* enable clock output */
141
142 /* Fields for TI K3 UART module */
143
144 #define MDR1_MODE_SELECT_FIELD_MASK BIT_MASK(3)
145 #define MDR1_MODE_SELECT_FIELD_SHIFT BIT_MASK(0)
146
147 /* Modes available for TI K3 UART module */
148
149 #define MDR1_STD_MODE (0)
150 #define MDR1_SIR_MODE (1)
151 #define MDR1_UART_16X (2)
152 #define MDR1_UART_13X (3)
153 #define MDR1_MIR_MODE (4)
154 #define MDR1_FIR_MODE (5)
155 #define MDR1_CIR_MODE (6)
156 #define MDR1_DISABLE (7)
157
158 /*
159 * Per PC16550D (Literature Number: SNLS378B):
160 *
161 * RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
162 * the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
163 * character in the RCVR FIFO or RCVR holding register, the
164 * RXRDY pin (29) will be low active. Once it is activated the
165 * RXRDY pin will go inactive when there are no more charac-
166 * ters in the FIFO or holding register.
167 *
168 * RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
169 * FCR3 = 1 and the trigger level or the timeout has been
170 * reached, the RXRDY pin will go low active. Once it is acti-
171 * vated it will go inactive when there are no more characters
172 * in the FIFO or holding register.
173 *
174 * TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
175 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
176 * ters in the XMIT FIFO or XMIT holding register, the TXRDY
177 * pin (24) will be low active. Once it is activated the TXRDY
178 * pin will go inactive after the first character is loaded into the
179 * XMIT FIFO or holding register.
180 *
181 * TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
182 * FCR3 = 1 and there are no characters in the XMIT FIFO, the
183 * TXRDY pin will go low active. This pin will become inactive
184 * when the XMIT FIFO is completely full.
185 */
186 #define FCR_MODE0 0x00 /* set receiver in mode 0 */
187 #define FCR_MODE1 0x08 /* set receiver in mode 1 */
188
189 /* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
190 #define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
191 #define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
192 #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
193 #define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
194
195 /*
196 * UART NS16750 supports 64 bytes FIFO, which can be enabled
197 * via the FCR register
198 */
199 #define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
200
201 /* constants for line control register */
202
203 #define LCR_CS5 0x00 /* 5 bits data size */
204 #define LCR_CS6 0x01 /* 6 bits data size */
205 #define LCR_CS7 0x02 /* 7 bits data size */
206 #define LCR_CS8 0x03 /* 8 bits data size */
207 #define LCR_2_STB 0x04 /* 2 stop bits */
208 #define LCR_1_STB 0x00 /* 1 stop bit */
209 #define LCR_PEN 0x08 /* parity enable */
210 #define LCR_PDIS 0x00 /* parity disable */
211 #define LCR_EPS 0x10 /* even parity select */
212 #define LCR_SP 0x20 /* stick parity select */
213 #define LCR_SBRK 0x40 /* break control bit */
214 #define LCR_DLAB 0x80 /* divisor latch access enable */
215
216 /* constants for the modem control register */
217
218 #define MCR_DTR 0x01 /* dtr output */
219 #define MCR_RTS 0x02 /* rts output */
220 #define MCR_OUT1 0x04 /* output #1 */
221 #define MCR_OUT2 0x08 /* output #2 */
222 #define MCR_LOOP 0x10 /* loop back */
223 #define MCR_AFCE 0x20 /* auto flow control enable */
224
225 /* constants for line status register */
226
227 #define LSR_RXRDY 0x01 /* receiver data available */
228 #define LSR_OE 0x02 /* overrun error */
229 #define LSR_PE 0x04 /* parity error */
230 #define LSR_FE 0x08 /* framing error */
231 #define LSR_BI 0x10 /* break interrupt */
232 #define LSR_EOB_MASK 0x1E /* Error or Break mask */
233 #define LSR_THRE 0x20 /* transmit holding register empty */
234 #define LSR_TEMT 0x40 /* transmitter empty */
235
236 /* constants for modem status register */
237
238 #define MSR_DCTS 0x01 /* cts change */
239 #define MSR_DDSR 0x02 /* dsr change */
240 #define MSR_DRI 0x04 /* ring change */
241 #define MSR_DDCD 0x08 /* data carrier change */
242 #define MSR_CTS 0x10 /* complement of cts */
243 #define MSR_DSR 0x20 /* complement of dsr */
244 #define MSR_RI 0x40 /* complement of ring signal */
245 #define MSR_DCD 0x80 /* complement of dcd */
246
247 #define THR(dev) (get_port(dev) + (REG_THR * reg_interval(dev)))
248 #define RDR(dev) (get_port(dev) + (REG_RDR * reg_interval(dev)))
249 #define BRDL(dev) (get_port(dev) + (REG_BRDL * reg_interval(dev)))
250 #define BRDH(dev) (get_port(dev) + (REG_BRDH * reg_interval(dev)))
251 #define IER(dev) (get_port(dev) + (REG_IER * reg_interval(dev)))
252 #define IIR(dev) (get_port(dev) + (REG_IIR * reg_interval(dev)))
253 #define FCR(dev) (get_port(dev) + (REG_FCR * reg_interval(dev)))
254 #define LCR(dev) (get_port(dev) + (REG_LCR * reg_interval(dev)))
255 #define MDC(dev) (get_port(dev) + (REG_MDC * reg_interval(dev)))
256 #define LSR(dev) (get_port(dev) + (REG_LSR * reg_interval(dev)))
257 #define MSR(dev) (get_port(dev) + (REG_MSR * reg_interval(dev)))
258 #define MDR1(dev) (get_port(dev) + (REG_MDR1 * reg_interval(dev)))
259 #define USR(dev) (get_port(dev) + REG_USR)
260 #define DLF(dev) (get_port(dev) + REG_DLF)
261 #define PCP(dev) (get_port(dev) + REG_PCP)
262
263 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
264 #define SRC_TRAN(dev) (get_port(dev) + REG_LPSS_SRC_TRAN)
265 #define CLR_SRC_TRAN(dev) (get_port(dev) + REG_LPSS_CLR_SRC_TRAN)
266 #define MST(dev) (get_port(dev) + REG_LPSS_MST)
267
268 #define UNMASK_LPSS_INT(chan) (BIT(chan) | (BIT(8) << chan)) /* unmask LPSS DMA Interrupt */
269 #endif
270
271 #define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
272
273 #ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
274 /* Register definitions (ITE_IT8XXX2) */
275 #define REG_ECSPMR 0x08 /* EC Serial port mode reg */
276
277 /* Fields for ITE IT8XXX2 UART module */
278 #define ECSPMR_ECHS 0x02 /* EC high speed select */
279
280 /* IT8XXX2 UART high speed baud rate settings */
281 #define UART_BAUDRATE_115200 115200
282 #define UART_BAUDRATE_230400 230400
283 #define UART_BAUDRATE_460800 460800
284 #define IT8XXX2_230400_DIVISOR 32770
285 #define IT8XXX2_460800_DIVISOR 32769
286
287 #define ECSPMR(dev) (get_port(dev) + REG_ECSPMR * reg_interval(dev))
288 #endif
289
290 #if defined(CONFIG_UART_ASYNC_API)
291 struct uart_ns16550_rx_dma_params {
292 const struct device *dma_dev;
293 uint8_t dma_channel;
294 struct dma_config dma_cfg;
295 struct dma_block_config active_dma_block;
296 uint8_t *buf;
297 size_t buf_len;
298 size_t offset;
299 size_t counter;
300 struct k_work_delayable timeout_work;
301 size_t timeout_us;
302 };
303
304 struct uart_ns16550_tx_dma_params {
305 const struct device *dma_dev;
306 uint8_t dma_channel;
307 struct dma_config dma_cfg;
308 struct dma_block_config active_dma_block;
309 const uint8_t *buf;
310 size_t buf_len;
311 struct k_work_delayable timeout_work;
312 size_t timeout_us;
313 };
314
315 struct uart_ns16550_async_data {
316 const struct device *uart_dev;
317 struct uart_ns16550_tx_dma_params tx_dma_params;
318 struct uart_ns16550_rx_dma_params rx_dma_params;
319 uint8_t *next_rx_buffer;
320 size_t next_rx_buffer_len;
321 uart_callback_t user_callback;
322 void *user_data;
323 };
324
325 static void uart_ns16550_async_rx_timeout(struct k_work *work);
326 static void uart_ns16550_async_tx_timeout(struct k_work *work);
327 #endif
328
329 /** Device config structure */
330 struct uart_ns16550_dev_config {
331 union {
332 DEVICE_MMIO_ROM;
333 uint32_t port;
334 };
335 uint32_t sys_clk_freq;
336 const struct device *clock_dev;
337 clock_control_subsys_t clock_subsys;
338 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
339 uart_irq_config_func_t irq_config_func;
340 #endif
341 #if UART_NS16550_PCP_ENABLED
342 uint32_t pcp;
343 #endif
344 uint8_t reg_interval;
345 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
346 struct pcie_dev *pcie;
347 #endif
348 #if defined(CONFIG_PINCTRL)
349 const struct pinctrl_dev_config *pincfg;
350 #endif
351 #if UART_NS16550_IOPORT_ENABLED
352 bool io_map;
353 #endif
354 #if UART_NS16550_RESET_ENABLED
355 struct reset_dt_spec reset_spec;
356 #endif
357 };
358
359 /** Device data structure */
360 struct uart_ns16550_dev_data {
361 DEVICE_MMIO_RAM;
362 struct uart_config uart_config;
363 struct k_spinlock lock;
364 uint8_t fifo_size;
365
366 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
367 uint8_t iir_cache; /**< cache of IIR since it clears when read */
368 uart_irq_callback_user_data_t cb; /**< Callback function pointer */
369 void *cb_data; /**< Callback function arg */
370 #endif
371
372 #if UART_NS16550_DLF_ENABLED
373 uint8_t dlf; /**< DLF value */
374 #endif
375
376 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
377 bool tx_stream_on;
378 #endif
379
380 #if defined(CONFIG_UART_ASYNC_API)
381 uint64_t phys_addr;
382 struct uart_ns16550_async_data async;
383 #endif
384 };
385
ns16550_outbyte(const struct uart_ns16550_dev_config * cfg,uintptr_t port,uint8_t val)386 static void ns16550_outbyte(const struct uart_ns16550_dev_config *cfg,
387 uintptr_t port, uint8_t val)
388 {
389 #if UART_NS16550_IOPORT_ENABLED
390 if (cfg->io_map) {
391 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
392 sys_out32(val, port);
393 } else {
394 sys_out8(val, port);
395 }
396 } else {
397 #else
398 {
399 #endif
400 /* MMIO mapped */
401 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
402 sys_write32(val, port);
403 } else {
404 sys_write8(val, port);
405 }
406 }
407 }
408
409 static uint8_t ns16550_inbyte(const struct uart_ns16550_dev_config *cfg,
410 uintptr_t port)
411 {
412 #if UART_NS16550_IOPORT_ENABLED
413 if (cfg->io_map) {
414 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
415 return sys_in32(port);
416 } else {
417 return sys_in8(port);
418 }
419 } else {
420 #else
421 {
422 #endif
423 /* MMIO mapped */
424 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
425 return sys_read32(port);
426 } else {
427 return sys_read8(port);
428 }
429 }
430 return 0;
431 }
432
433 __maybe_unused
434 static void ns16550_outword(const struct uart_ns16550_dev_config *cfg,
435 uintptr_t port, uint32_t val)
436 {
437 #if UART_NS16550_IOPORT_ENABLED
438 if (cfg->io_map) {
439 sys_out32(val, port);
440 } else {
441 #else
442 {
443 #endif
444 /* MMIO mapped */
445 sys_write32(val, port);
446 }
447 }
448
449 __maybe_unused
450 static uint32_t ns16550_inword(const struct uart_ns16550_dev_config *cfg,
451 uintptr_t port)
452 {
453 #if UART_NS16550_IOPORT_ENABLED
454 if (cfg->io_map) {
455 return sys_in32(port);
456 }
457 #endif
458 /* MMIO mapped */
459 return sys_read32(port);
460 }
461
462 static inline uint8_t reg_interval(const struct device *dev)
463 {
464 const struct uart_ns16550_dev_config *config = dev->config;
465
466 return config->reg_interval;
467 }
468
469 static inline uintptr_t get_port(const struct device *dev)
470 {
471 uintptr_t port;
472 #if UART_NS16550_IOPORT_ENABLED
473 const struct uart_ns16550_dev_config *config = dev->config;
474
475 if (config->io_map) {
476 port = config->port;
477 } else {
478 #else
479 {
480 #endif
481 port = DEVICE_MMIO_GET(dev);
482 }
483
484 return port;
485 }
486
487 static uint32_t get_uart_baudrate_divisor(const struct device *dev,
488 uint32_t baud_rate,
489 uint32_t pclk)
490 {
491 ARG_UNUSED(dev);
492 /*
493 * calculate baud rate divisor. a variant of
494 * (uint32_t)(pclk / (16.0 * baud_rate) + 0.5)
495 */
496 return ((pclk + (baud_rate << 3)) / baud_rate) >> 4;
497 }
498
499 #ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
500 static uint32_t get_ite_uart_baudrate_divisor(const struct device *dev,
501 uint32_t baud_rate,
502 uint32_t pclk)
503 {
504 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
505 uint32_t divisor = 0;
506
507 if (baud_rate > UART_BAUDRATE_115200) {
508 /* Baud rate divisor for high speed */
509 if (baud_rate == UART_BAUDRATE_230400) {
510 divisor = IT8XXX2_230400_DIVISOR;
511 } else if (baud_rate == UART_BAUDRATE_460800) {
512 divisor = IT8XXX2_460800_DIVISOR;
513 }
514 /*
515 * This bit indicates that the supported baud rate of
516 * UART1/UART2 can be up to 230.4k and 460.8k.
517 * Other bits are reserved and have no setting, so we
518 * directly write the ECSPMR register.
519 */
520 ns16550_outbyte(dev_cfg, ECSPMR(dev), ECSPMR_ECHS);
521 } else {
522 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
523 /* Set ECSPMR register as default */
524 ns16550_outbyte(dev_cfg, ECSPMR(dev), 0);
525 }
526
527 return divisor;
528 }
529 #endif
530
531 static inline int ns16550_read_char(const struct device *dev, unsigned char *c)
532 {
533 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
534
535 if ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0) {
536 *c = ns16550_inbyte(dev_cfg, RDR(dev));
537 return 0;
538 }
539
540 return -1;
541 }
542
543 static void set_baud_rate(const struct device *dev, uint32_t baud_rate, uint32_t pclk)
544 {
545 struct uart_ns16550_dev_data * const dev_data = dev->data;
546 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
547 uint32_t divisor; /* baud rate divisor */
548 uint8_t lcr_cache;
549
550 if ((baud_rate != 0U) && (pclk != 0U)) {
551 #ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
552 divisor = get_ite_uart_baudrate_divisor(dev, baud_rate, pclk);
553 #else
554 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
555 #endif
556 /* set the DLAB to access the baud rate divisor registers */
557 lcr_cache = ns16550_inbyte(dev_cfg, LCR(dev));
558 ns16550_outbyte(dev_cfg, LCR(dev), LCR_DLAB | lcr_cache);
559 ns16550_outbyte(dev_cfg, BRDL(dev), (unsigned char)(divisor & 0xff));
560 ns16550_outbyte(dev_cfg, BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
561
562 /* restore the DLAB to access the baud rate divisor registers */
563 ns16550_outbyte(dev_cfg, LCR(dev), lcr_cache);
564
565 dev_data->uart_config.baudrate = baud_rate;
566 }
567 }
568
569 static int uart_ns16550_configure(const struct device *dev,
570 const struct uart_config *cfg)
571 {
572 struct uart_ns16550_dev_data * const dev_data = dev->data;
573 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
574 uint8_t mdc = 0U, c;
575 uint32_t pclk = 0U;
576 int ret;
577
578 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
579
580 #if defined(CONFIG_PINCTRL)
581 if (dev_cfg->pincfg != NULL) {
582 pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);
583 }
584 #endif
585
586 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
587 dev_data->iir_cache = 0U;
588 #endif
589
590 #if UART_NS16550_DLF_ENABLED
591 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
592 #endif
593
594 #if UART_NS16550_PCP_ENABLED
595 uint32_t pcp = dev_cfg->pcp;
596
597 if (pcp) {
598 pcp |= PCP_EN;
599 ns16550_outbyte(dev_cfg, PCP(dev), pcp & ~PCP_UPDATE);
600 ns16550_outbyte(dev_cfg, PCP(dev), pcp | PCP_UPDATE);
601 }
602 #endif
603
604 #ifdef CONFIG_UART_NS16550_TI_K3
605 uint32_t mdr = ns16550_inbyte(dev_cfg, MDR1(dev));
606
607 mdr = ((mdr & ~MDR1_MODE_SELECT_FIELD_MASK) | ((((MDR1_STD_MODE) <<
608 MDR1_MODE_SELECT_FIELD_SHIFT)) & MDR1_MODE_SELECT_FIELD_MASK));
609 ns16550_outbyte(dev_cfg, MDR1(dev), mdr);
610 #endif
611 /*
612 * set clock frequency from clock_frequency property if valid,
613 * otherwise, get clock frequency from clock manager
614 */
615 if (dev_cfg->sys_clk_freq != 0U) {
616 pclk = dev_cfg->sys_clk_freq;
617 } else {
618 if (!device_is_ready(dev_cfg->clock_dev)) {
619 ret = -EINVAL;
620 goto out;
621 }
622
623 ret = clock_control_on(dev_cfg->clock_dev, dev_cfg->clock_subsys);
624 if (ret != 0 && ret != -EALREADY && ret != -ENOSYS) {
625 goto out;
626 }
627
628 if (clock_control_get_rate(dev_cfg->clock_dev,
629 dev_cfg->clock_subsys,
630 &pclk) != 0) {
631 ret = -EINVAL;
632 goto out;
633 }
634 }
635
636 set_baud_rate(dev, cfg->baudrate, pclk);
637
638 /* Local structure to hold temporary values to pass to ns16550_outbyte() */
639 struct uart_config uart_cfg;
640
641 switch (cfg->data_bits) {
642 case UART_CFG_DATA_BITS_5:
643 uart_cfg.data_bits = LCR_CS5;
644 break;
645 case UART_CFG_DATA_BITS_6:
646 uart_cfg.data_bits = LCR_CS6;
647 break;
648 case UART_CFG_DATA_BITS_7:
649 uart_cfg.data_bits = LCR_CS7;
650 break;
651 case UART_CFG_DATA_BITS_8:
652 uart_cfg.data_bits = LCR_CS8;
653 break;
654 default:
655 ret = -ENOTSUP;
656 goto out;
657 }
658
659 switch (cfg->stop_bits) {
660 case UART_CFG_STOP_BITS_1:
661 uart_cfg.stop_bits = LCR_1_STB;
662 break;
663 case UART_CFG_STOP_BITS_2:
664 uart_cfg.stop_bits = LCR_2_STB;
665 break;
666 default:
667 ret = -ENOTSUP;
668 goto out;
669 }
670
671 switch (cfg->parity) {
672 case UART_CFG_PARITY_NONE:
673 uart_cfg.parity = LCR_PDIS;
674 break;
675 case UART_CFG_PARITY_EVEN:
676 uart_cfg.parity = LCR_EPS;
677 break;
678 default:
679 ret = -ENOTSUP;
680 goto out;
681 }
682
683 dev_data->uart_config = *cfg;
684
685 /* data bits, stop bits, parity, clear DLAB */
686 ns16550_outbyte(dev_cfg, LCR(dev),
687 uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
688
689 mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
690 #if defined(CONFIG_UART_NS16550_VARIANT_NS16750) || \
691 defined(CONFIG_UART_NS16550_VARIANT_NS16950)
692 if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
693 mdc |= MCR_AFCE;
694 }
695 #endif
696
697 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
698
699 /*
700 * Program FIFO: enabled, mode 0 (set for compatibility with quark),
701 * generate the interrupt at 8th byte
702 * Clear TX and RX FIFO
703 */
704 ns16550_outbyte(dev_cfg, FCR(dev),
705 FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR
706 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
707 | FCR_FIFO_64
708 #endif
709 );
710
711 if ((ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_FE) == IIR_FE) {
712 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
713 dev_data->fifo_size = 64;
714 #elif defined(CONFIG_UART_NS16550_VARIANT_NS16950)
715 dev_data->fifo_size = 128;
716 #else
717 dev_data->fifo_size = 16;
718 #endif
719 } else {
720 dev_data->fifo_size = 1;
721 }
722
723 /* clear the port */
724 (void)ns16550_read_char(dev, &c);
725
726 /* disable interrupts */
727 ns16550_outbyte(dev_cfg, IER(dev), 0x00);
728 ret = 0;
729
730 out:
731 k_spin_unlock(&dev_data->lock, key);
732 return ret;
733 };
734
735 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
736 static int uart_ns16550_config_get(const struct device *dev,
737 struct uart_config *cfg)
738 {
739 struct uart_ns16550_dev_data *data = dev->data;
740
741 cfg->baudrate = data->uart_config.baudrate;
742 cfg->parity = data->uart_config.parity;
743 cfg->stop_bits = data->uart_config.stop_bits;
744 cfg->data_bits = data->uart_config.data_bits;
745 cfg->flow_ctrl = data->uart_config.flow_ctrl;
746
747 return 0;
748 }
749 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
750
751 #if UART_NS16550_RESET_ENABLED
752 /**
753 * @brief Toggle the reset UART line
754 *
755 * This routine is called to bring UART IP out of reset state.
756 *
757 * @param reset_spec Reset controller device configuration struct
758 *
759 * @return 0 if successful, failed otherwise
760 */
761 static int uart_reset_config(const struct reset_dt_spec *reset_spec)
762 {
763 int ret;
764
765 if (!device_is_ready(reset_spec->dev)) {
766 LOG_ERR("Reset controller device is not ready");
767 return -ENODEV;
768 }
769
770 ret = reset_line_toggle(reset_spec->dev, reset_spec->id);
771 if (ret != 0) {
772 LOG_ERR("UART toggle reset line failed");
773 return ret;
774 }
775
776 return 0;
777 }
778 #endif /* UART_NS16550_RESET_ENABLED */
779
780 #if (IS_ENABLED(CONFIG_UART_ASYNC_API))
781 static inline void async_timer_start(struct k_work_delayable *work, size_t timeout_us)
782 {
783 if ((timeout_us != SYS_FOREVER_US) && (timeout_us != 0)) {
784 k_work_reschedule(work, K_USEC(timeout_us));
785 }
786 }
787
788 #endif
789
790 /**
791 * @brief Initialize individual UART port
792 *
793 * This routine is called to reset the chip in a quiescent state.
794 *
795 * @param dev UART device struct
796 *
797 * @return 0 if successful, failed otherwise
798 */
799 static int uart_ns16550_init(const struct device *dev)
800 {
801 struct uart_ns16550_dev_data *data = dev->data;
802 const struct uart_ns16550_dev_config *dev_cfg = dev->config;
803 int ret;
804
805 ARG_UNUSED(dev_cfg);
806
807 #if UART_NS16550_RESET_ENABLED
808 /* Assert the UART reset line if it is defined. */
809 if (dev_cfg->reset_spec.dev != NULL) {
810 ret = uart_reset_config(&(dev_cfg->reset_spec));
811 if (ret != 0) {
812 return ret;
813 }
814 }
815 #endif
816
817 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
818 if (dev_cfg->pcie) {
819 struct pcie_bar mbar;
820
821 if (dev_cfg->pcie->bdf == PCIE_BDF_NONE) {
822 return -EINVAL;
823 }
824
825 pcie_probe_mbar(dev_cfg->pcie->bdf, 0, &mbar);
826 pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
827
828 device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size,
829 K_MEM_CACHE_NONE);
830 #if defined(CONFIG_UART_ASYNC_API)
831 if (data->async.tx_dma_params.dma_dev != NULL) {
832 pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true);
833 data->phys_addr = mbar.phys_addr;
834 }
835 #endif
836 } else
837 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */
838 {
839 #if UART_NS16550_IOPORT_ENABLED
840 /* Map directly from DTS */
841 if (!dev_cfg->io_map) {
842 #else
843 {
844 #endif
845 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
846 }
847 }
848 #if defined(CONFIG_UART_ASYNC_API)
849 if (data->async.tx_dma_params.dma_dev != NULL) {
850 data->async.next_rx_buffer = NULL;
851 data->async.next_rx_buffer_len = 0;
852 data->async.uart_dev = dev;
853 k_work_init_delayable(&data->async.rx_dma_params.timeout_work,
854 uart_ns16550_async_rx_timeout);
855 k_work_init_delayable(&data->async.tx_dma_params.timeout_work,
856 uart_ns16550_async_tx_timeout);
857 data->async.rx_dma_params.dma_cfg.head_block =
858 &data->async.rx_dma_params.active_dma_block;
859 data->async.tx_dma_params.dma_cfg.head_block =
860 &data->async.tx_dma_params.active_dma_block;
861 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
862 #if UART_NS16550_IOPORT_ENABLED
863 if (!dev_cfg->io_map)
864 #endif
865 {
866 uintptr_t base;
867
868 base = DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET;
869 dma_intel_lpss_set_base(data->async.tx_dma_params.dma_dev, base);
870 dma_intel_lpss_setup(data->async.tx_dma_params.dma_dev);
871 sys_write32((uint32_t)data->phys_addr,
872 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW);
873 sys_write32((uint32_t)(data->phys_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT),
874 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI);
875 }
876 #endif
877 }
878 #endif
879 ret = uart_ns16550_configure(dev, &data->uart_config);
880 if (ret != 0) {
881 return ret;
882 }
883
884 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
885 dev_cfg->irq_config_func(dev);
886 #endif
887
888 return 0;
889 }
890
891 /**
892 * @brief Poll the device for input.
893 *
894 * @param dev UART device struct
895 * @param c Pointer to character
896 *
897 * @return 0 if a character arrived, -1 if the input buffer if empty.
898 */
899 static int uart_ns16550_poll_in(const struct device *dev, unsigned char *c)
900 {
901 struct uart_ns16550_dev_data *data = dev->data;
902 int ret = -1;
903 k_spinlock_key_t key = k_spin_lock(&data->lock);
904
905 ret = ns16550_read_char(dev, c);
906
907 k_spin_unlock(&data->lock, key);
908
909 return ret;
910 }
911
912 /**
913 * @brief Output a character in polled mode.
914 *
915 * Checks if the transmitter is empty. If empty, a character is written to
916 * the data register.
917 *
918 * If the hardware flow control is enabled then the handshake signal CTS has to
919 * be asserted in order to send a character.
920 *
921 * @param dev UART device struct
922 * @param c Character to send
923 */
924 static void uart_ns16550_poll_out(const struct device *dev,
925 unsigned char c)
926 {
927 struct uart_ns16550_dev_data *data = dev->data;
928 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
929 k_spinlock_key_t key = k_spin_lock(&data->lock);
930
931 while ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_THRE) == 0) {
932 }
933
934 ns16550_outbyte(dev_cfg, THR(dev), c);
935
936 k_spin_unlock(&data->lock, key);
937 }
938
939 /**
940 * @brief Check if an error was received
941 *
942 * @param dev UART device struct
943 *
944 * @return one of UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
945 * UART_BREAK if an error was detected, 0 otherwise.
946 */
947 static int uart_ns16550_err_check(const struct device *dev)
948 {
949 struct uart_ns16550_dev_data *data = dev->data;
950 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
951 k_spinlock_key_t key = k_spin_lock(&data->lock);
952 int check = (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_EOB_MASK);
953
954 k_spin_unlock(&data->lock, key);
955
956 return check >> 1;
957 }
958
959 #if CONFIG_UART_INTERRUPT_DRIVEN
960
961 /**
962 * @brief Fill FIFO with data
963 *
964 * @param dev UART device struct
965 * @param tx_data Data to transmit
966 * @param size Number of bytes to send
967 *
968 * @return Number of bytes sent
969 */
970 static int uart_ns16550_fifo_fill(const struct device *dev,
971 const uint8_t *tx_data,
972 int size)
973 {
974 struct uart_ns16550_dev_data *data = dev->data;
975 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
976 int i;
977 k_spinlock_key_t key = k_spin_lock(&data->lock);
978
979 for (i = 0; (i < size) && (i < data->fifo_size); i++) {
980 ns16550_outbyte(dev_cfg, THR(dev), tx_data[i]);
981 }
982
983 k_spin_unlock(&data->lock, key);
984
985 return i;
986 }
987
988 /**
989 * @brief Read data from FIFO
990 *
991 * @param dev UART device struct
992 * @param rxData Data container
993 * @param size Container size
994 *
995 * @return Number of bytes read
996 */
997 static int uart_ns16550_fifo_read(const struct device *dev, uint8_t *rx_data,
998 const int size)
999 {
1000 struct uart_ns16550_dev_data *data = dev->data;
1001 int i;
1002 k_spinlock_key_t key = k_spin_lock(&data->lock);
1003
1004 for (i = 0; (i < size) && (ns16550_read_char(dev, &rx_data[i]) != -1); i++) {
1005 }
1006
1007 k_spin_unlock(&data->lock, key);
1008
1009 return i;
1010 }
1011
1012 /**
1013 * @brief Enable TX interrupt in IER
1014 *
1015 * @param dev UART device struct
1016 */
1017 static void uart_ns16550_irq_tx_enable(const struct device *dev)
1018 {
1019 struct uart_ns16550_dev_data *data = dev->data;
1020 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1021 k_spinlock_key_t key = k_spin_lock(&data->lock);
1022
1023 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
1024 struct uart_ns16550_dev_data *const dev_data = dev->data;
1025
1026 if (!dev_data->tx_stream_on) {
1027 dev_data->tx_stream_on = true;
1028 uint8_t num_cpu_states;
1029 const struct pm_state_info *cpu_states;
1030
1031 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
1032
1033 /*
1034 * Power state to be disabled. Some platforms have multiple
1035 * states and need to be given a constraint set according to
1036 * different states.
1037 */
1038 for (uint8_t i = 0U; i < num_cpu_states; i++) {
1039 pm_policy_state_lock_get(cpu_states[i].state, PM_ALL_SUBSTATES);
1040 }
1041 }
1042 #endif
1043 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE);
1044
1045 k_spin_unlock(&data->lock, key);
1046 }
1047
1048 /**
1049 * @brief Disable TX interrupt in IER
1050 *
1051 * @param dev UART device struct
1052 */
1053 static void uart_ns16550_irq_tx_disable(const struct device *dev)
1054 {
1055 struct uart_ns16550_dev_data *data = dev->data;
1056 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1057 k_spinlock_key_t key = k_spin_lock(&data->lock);
1058
1059 ns16550_outbyte(dev_cfg, IER(dev),
1060 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
1061
1062 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
1063 struct uart_ns16550_dev_data *const dev_data = dev->data;
1064
1065 if (dev_data->tx_stream_on) {
1066 dev_data->tx_stream_on = false;
1067 uint8_t num_cpu_states;
1068 const struct pm_state_info *cpu_states;
1069
1070 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
1071
1072 /*
1073 * Power state to be enabled. Some platforms have multiple
1074 * states and need to be given a constraint release according
1075 * to different states.
1076 */
1077 for (uint8_t i = 0U; i < num_cpu_states; i++) {
1078 pm_policy_state_lock_put(cpu_states[i].state, PM_ALL_SUBSTATES);
1079 }
1080 }
1081 #endif
1082 k_spin_unlock(&data->lock, key);
1083 }
1084
1085 /**
1086 * @brief Check if Tx IRQ has been raised
1087 *
1088 * @param dev UART device struct
1089 *
1090 * @return 1 if an IRQ is ready, 0 otherwise
1091 */
1092 static int uart_ns16550_irq_tx_ready(const struct device *dev)
1093 {
1094 struct uart_ns16550_dev_data *data = dev->data;
1095 k_spinlock_key_t key = k_spin_lock(&data->lock);
1096
1097 int ret = ((IIRC(dev) & IIR_ID) == IIR_THRE) ? 1 : 0;
1098
1099 k_spin_unlock(&data->lock, key);
1100
1101 return ret;
1102 }
1103
1104 /**
1105 * @brief Check if nothing remains to be transmitted
1106 *
1107 * @param dev UART device struct
1108 *
1109 * @return 1 if nothing remains to be transmitted, 0 otherwise
1110 */
1111 static int uart_ns16550_irq_tx_complete(const struct device *dev)
1112 {
1113 struct uart_ns16550_dev_data *data = dev->data;
1114 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1115 k_spinlock_key_t key = k_spin_lock(&data->lock);
1116
1117 int ret = ((ns16550_inbyte(dev_cfg, LSR(dev)) & (LSR_TEMT | LSR_THRE))
1118 == (LSR_TEMT | LSR_THRE)) ? 1 : 0;
1119
1120 k_spin_unlock(&data->lock, key);
1121
1122 return ret;
1123 }
1124
1125 /**
1126 * @brief Enable RX interrupt in IER
1127 *
1128 * @param dev UART device struct
1129 */
1130 static void uart_ns16550_irq_rx_enable(const struct device *dev)
1131 {
1132 struct uart_ns16550_dev_data *data = dev->data;
1133 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1134 k_spinlock_key_t key = k_spin_lock(&data->lock);
1135
1136 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_RXRDY);
1137
1138 k_spin_unlock(&data->lock, key);
1139 }
1140
1141 /**
1142 * @brief Disable RX interrupt in IER
1143 *
1144 * @param dev UART device struct
1145 */
1146 static void uart_ns16550_irq_rx_disable(const struct device *dev)
1147 {
1148 struct uart_ns16550_dev_data *data = dev->data;
1149 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1150 k_spinlock_key_t key = k_spin_lock(&data->lock);
1151
1152 ns16550_outbyte(dev_cfg, IER(dev),
1153 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_RXRDY));
1154
1155 k_spin_unlock(&data->lock, key);
1156 }
1157
1158 /**
1159 * @brief Check if Rx IRQ has been raised
1160 *
1161 * @param dev UART device struct
1162 *
1163 * @return 1 if an IRQ is ready, 0 otherwise
1164 */
1165 static int uart_ns16550_irq_rx_ready(const struct device *dev)
1166 {
1167 struct uart_ns16550_dev_data *data = dev->data;
1168 k_spinlock_key_t key = k_spin_lock(&data->lock);
1169
1170 int ret = ((IIRC(dev) & IIR_ID) == IIR_RBRF) ? 1 : 0;
1171
1172 k_spin_unlock(&data->lock, key);
1173
1174 return ret;
1175 }
1176
1177 /**
1178 * @brief Enable error interrupt in IER
1179 *
1180 * @param dev UART device struct
1181 */
1182 static void uart_ns16550_irq_err_enable(const struct device *dev)
1183 {
1184 struct uart_ns16550_dev_data *data = dev->data;
1185 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1186 k_spinlock_key_t key = k_spin_lock(&data->lock);
1187
1188 ns16550_outbyte(dev_cfg, IER(dev),
1189 ns16550_inbyte(dev_cfg, IER(dev)) | IER_LSR);
1190
1191 k_spin_unlock(&data->lock, key);
1192 }
1193
1194 /**
1195 * @brief Disable error interrupt in IER
1196 *
1197 * @param dev UART device struct
1198 *
1199 * @return 1 if an IRQ is ready, 0 otherwise
1200 */
1201 static void uart_ns16550_irq_err_disable(const struct device *dev)
1202 {
1203 struct uart_ns16550_dev_data *data = dev->data;
1204 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1205 k_spinlock_key_t key = k_spin_lock(&data->lock);
1206
1207 ns16550_outbyte(dev_cfg, IER(dev),
1208 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_LSR));
1209
1210 k_spin_unlock(&data->lock, key);
1211 }
1212
1213 /**
1214 * @brief Check if any IRQ is pending
1215 *
1216 * @param dev UART device struct
1217 *
1218 * @return 1 if an IRQ is pending, 0 otherwise
1219 */
1220 static int uart_ns16550_irq_is_pending(const struct device *dev)
1221 {
1222 struct uart_ns16550_dev_data *data = dev->data;
1223 k_spinlock_key_t key = k_spin_lock(&data->lock);
1224
1225 int ret = (!(IIRC(dev) & IIR_NIP)) ? 1 : 0;
1226
1227 k_spin_unlock(&data->lock, key);
1228
1229 return ret;
1230 }
1231
1232 /**
1233 * @brief Update cached contents of IIR
1234 *
1235 * @param dev UART device struct
1236 *
1237 * @return Always 1
1238 */
1239 static int uart_ns16550_irq_update(const struct device *dev)
1240 {
1241 struct uart_ns16550_dev_data *data = dev->data;
1242 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1243 k_spinlock_key_t key = k_spin_lock(&data->lock);
1244
1245 IIRC(dev) = ns16550_inbyte(dev_cfg, IIR(dev));
1246
1247 k_spin_unlock(&data->lock, key);
1248
1249 return 1;
1250 }
1251
1252 /**
1253 * @brief Set the callback function pointer for IRQ.
1254 *
1255 * @param dev UART device struct
1256 * @param cb Callback function pointer.
1257 */
1258 static void uart_ns16550_irq_callback_set(const struct device *dev,
1259 uart_irq_callback_user_data_t cb,
1260 void *cb_data)
1261 {
1262 struct uart_ns16550_dev_data * const dev_data = dev->data;
1263 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1264
1265 dev_data->cb = cb;
1266 dev_data->cb_data = cb_data;
1267
1268 k_spin_unlock(&dev_data->lock, key);
1269 }
1270
1271 /**
1272 * @brief Interrupt service routine.
1273 *
1274 * This simply calls the callback function, if one exists.
1275 *
1276 * @param arg Argument to ISR.
1277 */
1278 static void uart_ns16550_isr(const struct device *dev)
1279 {
1280 struct uart_ns16550_dev_data * const dev_data = dev->data;
1281 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1282
1283 if (dev_data->cb) {
1284 dev_data->cb(dev, dev_data->cb_data);
1285 } else if ((IS_ENABLED(CONFIG_UART_NS16550_DW8250_DW_APB)) &&
1286 ((ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_MASK) == IIR_BUSY)) {
1287 /*
1288 * The Synopsys DesignWare 8250 has an extra feature whereby
1289 * it detects if the LCR is written whilst busy.
1290 * If it is, then a busy detect interrupt is raised,
1291 * the uart status register need to be read.
1292 */
1293 ns16550_inword(dev_cfg, USR(dev));
1294 }
1295
1296 #if (IS_ENABLED(CONFIG_UART_ASYNC_API))
1297 if (dev_data->async.tx_dma_params.dma_dev != NULL) {
1298 const struct uart_ns16550_dev_config * const config = dev->config;
1299 uint8_t IIR_status = ns16550_inbyte(config, IIR(dev));
1300 #if (IS_ENABLED(CONFIG_UART_NS16550_INTEL_LPSS_DMA))
1301 uint32_t dma_status = ns16550_inword(config, SRC_TRAN(dev));
1302
1303 if (dma_status & BIT(dev_data->async.rx_dma_params.dma_channel)) {
1304 async_timer_start(&dev_data->async.rx_dma_params.timeout_work,
1305 dev_data->async.rx_dma_params.timeout_us);
1306 ns16550_outword(config, CLR_SRC_TRAN(dev),
1307 BIT(dev_data->async.rx_dma_params.dma_channel));
1308 return;
1309 }
1310 dma_intel_lpss_isr(dev_data->async.rx_dma_params.dma_dev);
1311 #endif
1312 if (IIR_status & IIR_RBRF) {
1313 async_timer_start(&dev_data->async.rx_dma_params.timeout_work,
1314 dev_data->async.rx_dma_params.timeout_us);
1315 return;
1316 }
1317 }
1318 #endif
1319
1320 #ifdef CONFIG_UART_NS16550_WA_ISR_REENABLE_INTERRUPT
1321 uint8_t cached_ier = ns16550_inbyte(dev_cfg, IER(dev));
1322
1323 ns16550_outbyte(dev_cfg, IER(dev), 0U);
1324 ns16550_outbyte(dev_cfg, IER(dev), cached_ier);
1325 #endif
1326 }
1327
1328 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1329
1330 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1331
1332 /**
1333 * @brief Manipulate line control for UART.
1334 *
1335 * @param dev UART device struct
1336 * @param ctrl The line control to be manipulated
1337 * @param val Value to set the line control
1338 *
1339 * @return 0 if successful, failed otherwise
1340 */
1341 static int uart_ns16550_line_ctrl_set(const struct device *dev,
1342 uint32_t ctrl, uint32_t val)
1343 {
1344 struct uart_ns16550_dev_data *data = dev->data;
1345 const struct uart_ns16550_dev_config *const dev_cfg = dev->config;
1346 uint32_t mdc, chg, pclk = 0U;
1347 k_spinlock_key_t key;
1348
1349 if (dev_cfg->sys_clk_freq != 0U) {
1350 pclk = dev_cfg->sys_clk_freq;
1351 } else {
1352 if (device_is_ready(dev_cfg->clock_dev)) {
1353 clock_control_get_rate(dev_cfg->clock_dev, dev_cfg->clock_subsys, &pclk);
1354 }
1355 }
1356
1357 switch (ctrl) {
1358 case UART_LINE_CTRL_BAUD_RATE:
1359 set_baud_rate(dev, val, pclk);
1360 return 0;
1361
1362 case UART_LINE_CTRL_RTS:
1363 case UART_LINE_CTRL_DTR:
1364 key = k_spin_lock(&data->lock);
1365 mdc = ns16550_inbyte(dev_cfg, MDC(dev));
1366
1367 if (ctrl == UART_LINE_CTRL_RTS) {
1368 chg = MCR_RTS;
1369 } else {
1370 chg = MCR_DTR;
1371 }
1372
1373 if (val) {
1374 mdc |= chg;
1375 } else {
1376 mdc &= ~(chg);
1377 }
1378 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
1379 k_spin_unlock(&data->lock, key);
1380 return 0;
1381 }
1382
1383 return -ENOTSUP;
1384 }
1385
1386 #endif /* CONFIG_UART_NS16550_LINE_CTRL */
1387
1388 #ifdef CONFIG_UART_NS16550_DRV_CMD
1389
1390 /**
1391 * @brief Send extra command to driver
1392 *
1393 * @param dev UART device struct
1394 * @param cmd Command to driver
1395 * @param p Parameter to the command
1396 *
1397 * @return 0 if successful, failed otherwise
1398 */
1399 static int uart_ns16550_drv_cmd(const struct device *dev, uint32_t cmd,
1400 uint32_t p)
1401 {
1402 #if UART_NS16550_DLF_ENABLED
1403 if (cmd == CMD_SET_DLF) {
1404 struct uart_ns16550_dev_data * const dev_data = dev->data;
1405 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1406 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1407
1408 dev_data->dlf = p;
1409 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
1410 k_spin_unlock(&dev_data->lock, key);
1411 return 0;
1412 }
1413 #endif
1414
1415 return -ENOTSUP;
1416 }
1417
1418 #endif /* CONFIG_UART_NS16550_DRV_CMD */
1419
1420 #if (IS_ENABLED(CONFIG_UART_ASYNC_API))
1421 static void async_user_callback(const struct device *dev, struct uart_event *evt)
1422 {
1423 const struct uart_ns16550_dev_data *data = dev->data;
1424
1425 if (data->async.user_callback) {
1426 data->async.user_callback(dev, evt, data->async.user_data);
1427 }
1428 }
1429
1430 #if UART_NS16550_DMAS_ENABLED
1431 static void async_evt_tx_done(struct device *dev)
1432 {
1433 struct uart_ns16550_dev_data *data = dev->data;
1434 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1435
1436 (void)k_work_cancel_delayable(&data->async.tx_dma_params.timeout_work);
1437
1438 struct uart_event event = {
1439 .type = UART_TX_DONE,
1440 .data.tx.buf = tx_params->buf,
1441 .data.tx.len = tx_params->buf_len
1442 };
1443
1444 tx_params->buf = NULL;
1445 tx_params->buf_len = 0U;
1446
1447 async_user_callback(dev, &event);
1448 }
1449 #endif
1450
1451 static void async_evt_rx_rdy(const struct device *dev)
1452 {
1453 struct uart_ns16550_dev_data *data = dev->data;
1454 struct uart_ns16550_rx_dma_params *dma_params = &data->async.rx_dma_params;
1455
1456 struct uart_event event = {
1457 .type = UART_RX_RDY,
1458 .data.rx.buf = dma_params->buf,
1459 .data.rx.len = dma_params->counter - dma_params->offset,
1460 .data.rx.offset = dma_params->offset
1461 };
1462
1463 dma_params->offset = dma_params->counter;
1464
1465 if (event.data.rx.len > 0) {
1466 async_user_callback(dev, &event);
1467 }
1468 }
1469
1470 static void async_evt_rx_buf_release(const struct device *dev)
1471 {
1472 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)dev->data;
1473 struct uart_event evt = {
1474 .type = UART_RX_BUF_RELEASED,
1475 .data.rx_buf.buf = data->async.rx_dma_params.buf
1476 };
1477
1478 async_user_callback(dev, &evt);
1479 data->async.rx_dma_params.buf = NULL;
1480 data->async.rx_dma_params.buf_len = 0U;
1481 data->async.rx_dma_params.offset = 0U;
1482 data->async.rx_dma_params.counter = 0U;
1483 }
1484
1485 static void async_evt_rx_buf_request(const struct device *dev)
1486 {
1487 struct uart_event evt = {
1488 .type = UART_RX_BUF_REQUEST
1489 };
1490 async_user_callback(dev, &evt);
1491 }
1492
1493 static void uart_ns16550_async_rx_flush(const struct device *dev)
1494 {
1495 struct uart_ns16550_dev_data *data = dev->data;
1496 struct uart_ns16550_rx_dma_params *dma_params = &data->async.rx_dma_params;
1497 struct dma_status status;
1498
1499 dma_get_status(dma_params->dma_dev,
1500 dma_params->dma_channel,
1501 &status);
1502
1503 const int rx_count = dma_params->buf_len - status.pending_length;
1504
1505 if (rx_count > dma_params->counter) {
1506 dma_params->counter = rx_count;
1507 async_evt_rx_rdy(dev);
1508 }
1509 }
1510
1511 static int uart_ns16550_rx_disable(const struct device *dev)
1512 {
1513 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)dev->data;
1514 struct uart_ns16550_rx_dma_params *dma_params = &data->async.rx_dma_params;
1515 k_spinlock_key_t key = k_spin_lock(&data->lock);
1516 int ret = 0;
1517
1518 if (!device_is_ready(dma_params->dma_dev)) {
1519 ret = -ENODEV;
1520 goto out;
1521 }
1522
1523 (void)k_work_cancel_delayable(&data->async.rx_dma_params.timeout_work);
1524
1525 if (dma_params->buf && (dma_params->buf_len > 0)) {
1526 uart_ns16550_async_rx_flush(dev);
1527 async_evt_rx_buf_release(dev);
1528 if (data->async.next_rx_buffer != NULL) {
1529 dma_params->buf = data->async.next_rx_buffer;
1530 dma_params->buf_len = data->async.next_rx_buffer_len;
1531 data->async.next_rx_buffer = NULL;
1532 data->async.next_rx_buffer_len = 0;
1533 async_evt_rx_buf_release(dev);
1534 }
1535 }
1536 ret = dma_stop(dma_params->dma_dev,
1537 dma_params->dma_channel);
1538
1539 struct uart_event event = {
1540 .type = UART_RX_DISABLED
1541 };
1542
1543 async_user_callback(dev, &event);
1544
1545 out:
1546 k_spin_unlock(&data->lock, key);
1547 return ret;
1548 }
1549
1550 static void prepare_rx_dma_block_config(const struct device *dev)
1551 {
1552 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)dev->data;
1553 struct uart_ns16550_rx_dma_params *rx_dma_params = &data->async.rx_dma_params;
1554
1555 assert(rx_dma_params->buf != NULL);
1556 assert(rx_dma_params->buf_len > 0);
1557
1558 struct dma_block_config *head_block_config = &rx_dma_params->active_dma_block;
1559
1560 head_block_config->dest_address = (uintptr_t)rx_dma_params->buf;
1561 head_block_config->source_address = data->phys_addr;
1562 head_block_config->block_size = rx_dma_params->buf_len;
1563 }
1564
1565 #if UART_NS16550_DMAS_ENABLED
1566 static void dma_callback(const struct device *dev, void *user_data, uint32_t channel,
1567 int status)
1568 {
1569 struct device *uart_dev = (struct device *)user_data;
1570 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)uart_dev->data;
1571 struct uart_ns16550_rx_dma_params *rx_params = &data->async.rx_dma_params;
1572 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1573
1574 if (channel == tx_params->dma_channel) {
1575 async_evt_tx_done(uart_dev);
1576 } else if (channel == rx_params->dma_channel) {
1577
1578 rx_params->counter = rx_params->buf_len;
1579
1580 async_evt_rx_rdy(uart_dev);
1581 async_evt_rx_buf_release(uart_dev);
1582
1583 rx_params->buf = data->async.next_rx_buffer;
1584 rx_params->buf_len = data->async.next_rx_buffer_len;
1585 data->async.next_rx_buffer = NULL;
1586 data->async.next_rx_buffer_len = 0U;
1587
1588 if (rx_params->buf != NULL &&
1589 rx_params->buf_len > 0) {
1590 dma_reload(dev, rx_params->dma_channel, data->phys_addr,
1591 (uintptr_t)rx_params->buf, rx_params->buf_len);
1592 dma_start(dev, rx_params->dma_channel);
1593 async_evt_rx_buf_request(uart_dev);
1594 } else {
1595 uart_ns16550_rx_disable(uart_dev);
1596 }
1597 }
1598 }
1599 #endif
1600
1601 static int uart_ns16550_callback_set(const struct device *dev, uart_callback_t callback,
1602 void *user_data)
1603 {
1604 struct uart_ns16550_dev_data *data = dev->data;
1605
1606 data->async.user_callback = callback;
1607 data->async.user_data = user_data;
1608
1609 return 0;
1610 }
1611
1612 static int uart_ns16550_tx(const struct device *dev, const uint8_t *buf, size_t len,
1613 int32_t timeout_us)
1614 {
1615 struct uart_ns16550_dev_data *data = dev->data;
1616 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1617 k_spinlock_key_t key = k_spin_lock(&data->lock);
1618 int ret = 0;
1619
1620 if (!device_is_ready(tx_params->dma_dev)) {
1621 ret = -ENODEV;
1622 goto out;
1623 }
1624
1625 tx_params->buf = buf;
1626 tx_params->buf_len = len;
1627 tx_params->active_dma_block.source_address = (uintptr_t)buf;
1628 tx_params->active_dma_block.dest_address = data->phys_addr;
1629 tx_params->active_dma_block.block_size = len;
1630 tx_params->active_dma_block.next_block = NULL;
1631
1632 ret = dma_config(tx_params->dma_dev,
1633 tx_params->dma_channel,
1634 (struct dma_config *)&tx_params->dma_cfg);
1635
1636 if (ret == 0) {
1637 ret = dma_start(tx_params->dma_dev,
1638 tx_params->dma_channel);
1639 if (ret) {
1640 ret = -EIO;
1641 goto out;
1642 }
1643 async_timer_start(&data->async.tx_dma_params.timeout_work, timeout_us);
1644 }
1645
1646 out:
1647 k_spin_unlock(&data->lock, key);
1648 return ret;
1649 }
1650
1651 static int uart_ns16550_tx_abort(const struct device *dev)
1652 {
1653 struct uart_ns16550_dev_data *data = dev->data;
1654 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1655 struct dma_status status;
1656 int ret = 0;
1657 size_t bytes_tx;
1658
1659 k_spinlock_key_t key = k_spin_lock(&data->lock);
1660
1661 if (!device_is_ready(tx_params->dma_dev)) {
1662 ret = -ENODEV;
1663 goto out;
1664 }
1665
1666 (void)k_work_cancel_delayable(&data->async.tx_dma_params.timeout_work);
1667
1668 ret = dma_stop(tx_params->dma_dev, tx_params->dma_channel);
1669 dma_get_status(tx_params->dma_dev,
1670 tx_params->dma_channel,
1671 &status);
1672 bytes_tx = tx_params->buf_len - status.pending_length;
1673
1674 if (ret == 0) {
1675 struct uart_event tx_aborted_event = {
1676 .type = UART_TX_ABORTED,
1677 .data.tx.buf = tx_params->buf,
1678 .data.tx.len = bytes_tx
1679 };
1680 async_user_callback(dev, &tx_aborted_event);
1681 }
1682 out:
1683 k_spin_unlock(&data->lock, key);
1684 return ret;
1685 }
1686
1687 static int uart_ns16550_rx_enable(const struct device *dev, uint8_t *buf, const size_t len,
1688 const int32_t timeout_us)
1689 {
1690 struct uart_ns16550_dev_data *data = dev->data;
1691 const struct uart_ns16550_dev_config *config = dev->config;
1692 struct uart_ns16550_rx_dma_params *rx_dma_params = &data->async.rx_dma_params;
1693 int ret = 0;
1694 k_spinlock_key_t key = k_spin_lock(&data->lock);
1695
1696 if (!device_is_ready(rx_dma_params->dma_dev)) {
1697 ret = -ENODEV;
1698 goto out;
1699 }
1700
1701 rx_dma_params->timeout_us = timeout_us;
1702 rx_dma_params->buf = buf;
1703 rx_dma_params->buf_len = len;
1704
1705 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
1706 ns16550_outword(config, MST(dev), UNMASK_LPSS_INT(rx_dma_params->dma_channel));
1707 #else
1708 ns16550_outbyte(config, IER(dev),
1709 (ns16550_inbyte(config, IER(dev)) | IER_RXRDY));
1710 ns16550_outbyte(config, FCR(dev), FCR_FIFO);
1711 #endif
1712 prepare_rx_dma_block_config(dev);
1713 dma_config(rx_dma_params->dma_dev,
1714 rx_dma_params->dma_channel,
1715 (struct dma_config *)&rx_dma_params->dma_cfg);
1716 dma_start(rx_dma_params->dma_dev, rx_dma_params->dma_channel);
1717 async_evt_rx_buf_request(dev);
1718 out:
1719 k_spin_unlock(&data->lock, key);
1720 return ret;
1721 }
1722
1723 static int uart_ns16550_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
1724 {
1725 struct uart_ns16550_dev_data *data = dev->data;
1726
1727 assert(data->async.next_rx_buffer == NULL);
1728 assert(data->async.next_rx_buffer_len == 0);
1729 data->async.next_rx_buffer = buf;
1730 data->async.next_rx_buffer_len = len;
1731
1732 return 0;
1733 }
1734
1735 static void uart_ns16550_async_rx_timeout(struct k_work *work)
1736 {
1737 struct k_work_delayable *work_delay = CONTAINER_OF(work, struct k_work_delayable, work);
1738 struct uart_ns16550_rx_dma_params *rx_params =
1739 CONTAINER_OF(work_delay, struct uart_ns16550_rx_dma_params,
1740 timeout_work);
1741 struct uart_ns16550_async_data *async_data =
1742 CONTAINER_OF(rx_params, struct uart_ns16550_async_data,
1743 rx_dma_params);
1744 const struct device *dev = async_data->uart_dev;
1745
1746 uart_ns16550_async_rx_flush(dev);
1747
1748 }
1749
1750 static void uart_ns16550_async_tx_timeout(struct k_work *work)
1751 {
1752 struct k_work_delayable *work_delay = CONTAINER_OF(work, struct k_work_delayable, work);
1753 struct uart_ns16550_tx_dma_params *tx_params =
1754 CONTAINER_OF(work_delay, struct uart_ns16550_tx_dma_params,
1755 timeout_work);
1756 struct uart_ns16550_async_data *async_data =
1757 CONTAINER_OF(tx_params, struct uart_ns16550_async_data,
1758 tx_dma_params);
1759 const struct device *dev = async_data->uart_dev;
1760
1761 (void)uart_ns16550_tx_abort(dev);
1762 }
1763
1764 #endif /* CONFIG_UART_ASYNC_API */
1765
1766 static DEVICE_API(uart, uart_ns16550_driver_api) = {
1767 .poll_in = uart_ns16550_poll_in,
1768 .poll_out = uart_ns16550_poll_out,
1769 .err_check = uart_ns16550_err_check,
1770 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
1771 .configure = uart_ns16550_configure,
1772 .config_get = uart_ns16550_config_get,
1773 #endif
1774 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1775
1776 .fifo_fill = uart_ns16550_fifo_fill,
1777 .fifo_read = uart_ns16550_fifo_read,
1778 .irq_tx_enable = uart_ns16550_irq_tx_enable,
1779 .irq_tx_disable = uart_ns16550_irq_tx_disable,
1780 .irq_tx_ready = uart_ns16550_irq_tx_ready,
1781 .irq_tx_complete = uart_ns16550_irq_tx_complete,
1782 .irq_rx_enable = uart_ns16550_irq_rx_enable,
1783 .irq_rx_disable = uart_ns16550_irq_rx_disable,
1784 .irq_rx_ready = uart_ns16550_irq_rx_ready,
1785 .irq_err_enable = uart_ns16550_irq_err_enable,
1786 .irq_err_disable = uart_ns16550_irq_err_disable,
1787 .irq_is_pending = uart_ns16550_irq_is_pending,
1788 .irq_update = uart_ns16550_irq_update,
1789 .irq_callback_set = uart_ns16550_irq_callback_set,
1790
1791 #endif
1792
1793 #ifdef CONFIG_UART_ASYNC_API
1794 .callback_set = uart_ns16550_callback_set,
1795 .tx = uart_ns16550_tx,
1796 .tx_abort = uart_ns16550_tx_abort,
1797 .rx_enable = uart_ns16550_rx_enable,
1798 .rx_disable = uart_ns16550_rx_disable,
1799 .rx_buf_rsp = uart_ns16550_rx_buf_rsp,
1800 #endif
1801
1802 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1803 .line_ctrl_set = uart_ns16550_line_ctrl_set,
1804 #endif
1805
1806 #ifdef CONFIG_UART_NS16550_DRV_CMD
1807 .drv_cmd = uart_ns16550_drv_cmd,
1808 #endif
1809 };
1810
1811 #define UART_NS16550_IRQ_FLAGS(n) \
1812 COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, sense), \
1813 (DT_INST_IRQ(n, sense)), \
1814 (0))
1815
1816 /* IO-port or MMIO based UART */
1817 #define UART_NS16550_IRQ_CONFIG(n) \
1818 static void uart_ns16550_irq_config_func##n(const struct device *dev) \
1819 { \
1820 ARG_UNUSED(dev); \
1821 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
1822 uart_ns16550_isr, DEVICE_DT_INST_GET(n), \
1823 UART_NS16550_IRQ_FLAGS(n)); \
1824 irq_enable(DT_INST_IRQN(n)); \
1825 }
1826
1827 /* PCI(e) with auto IRQ detection */
1828 #define UART_NS16550_IRQ_CONFIG_PCIE(n) \
1829 static void uart_ns16550_irq_config_func##n(const struct device *dev) \
1830 { \
1831 BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
1832 "Only runtime IRQ configuration is supported"); \
1833 BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
1834 "NS16550 PCIe requires dynamic interrupts"); \
1835 const struct uart_ns16550_dev_config *dev_cfg = dev->config; \
1836 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1837 if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
1838 return; \
1839 } \
1840 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
1841 DT_INST_IRQ(n, priority), \
1842 (void (*)(const void *))uart_ns16550_isr, \
1843 DEVICE_DT_INST_GET(n), \
1844 UART_NS16550_IRQ_FLAGS(n)); \
1845 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
1846 }
1847
1848 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1849 #define DEV_CONFIG_IRQ_FUNC_INIT(n) \
1850 .irq_config_func = uart_ns16550_irq_config_func##n,
1851 #define UART_NS16550_IRQ_FUNC_DECLARE(n) \
1852 static void uart_ns16550_irq_config_func##n(const struct device *dev);
1853 #define UART_NS16550_IRQ_FUNC_DEFINE(n) \
1854 UART_NS16550_IRQ_CONFIG(n)
1855
1856 #define DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n) \
1857 .irq_config_func = uart_ns16550_irq_config_func##n,
1858 #define UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n) \
1859 static void uart_ns16550_irq_config_func##n(const struct device *dev);
1860 #define UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n) \
1861 UART_NS16550_IRQ_CONFIG_PCIE(n)
1862 #else
1863 /* !CONFIG_UART_INTERRUPT_DRIVEN */
1864 #define DEV_CONFIG_IRQ_FUNC_INIT(n)
1865 #define UART_NS16550_IRQ_FUNC_DECLARE(n)
1866 #define UART_NS16550_IRQ_FUNC_DEFINE(n)
1867
1868 #define DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n)
1869 #define UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n)
1870 #define UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n)
1871 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1872
1873 #ifdef CONFIG_UART_ASYNC_API
1874 #define DMA_PARAMS(n) \
1875 .async.tx_dma_params = { \
1876 .dma_dev = \
1877 DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
1878 .dma_channel = \
1879 DT_INST_DMAS_CELL_BY_NAME(n, tx, channel), \
1880 .dma_cfg = { \
1881 .source_burst_length = 1, \
1882 .dest_burst_length = 1, \
1883 .source_data_size = 1, \
1884 .dest_data_size = 1, \
1885 .complete_callback_en = 0, \
1886 .error_callback_dis = 1, \
1887 .block_count = 1, \
1888 .channel_direction = MEMORY_TO_PERIPHERAL, \
1889 .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, channel), \
1890 .dma_callback = dma_callback, \
1891 .user_data = (void *)DEVICE_DT_INST_GET(n) \
1892 }, \
1893 }, \
1894 .async.rx_dma_params = { \
1895 .dma_dev = \
1896 DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)), \
1897 .dma_channel = \
1898 DT_INST_DMAS_CELL_BY_NAME(n, rx, channel), \
1899 .dma_cfg = { \
1900 .source_burst_length = 1, \
1901 .dest_burst_length = 1, \
1902 .source_data_size = 1, \
1903 .dest_data_size = 1, \
1904 .complete_callback_en = 0, \
1905 .error_callback_dis = 1, \
1906 .block_count = 1, \
1907 .channel_direction = PERIPHERAL_TO_MEMORY, \
1908 .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, channel), \
1909 .dma_callback = dma_callback, \
1910 .user_data = (void *)DEVICE_DT_INST_GET(n) \
1911 }, \
1912 }, \
1913 COND_CODE_0(DT_INST_ON_BUS(n, pcie), \
1914 (.phys_addr = DT_INST_REG_ADDR(n),), ())
1915
1916 #define DMA_PARAMS_NULL(n) \
1917 .async.tx_dma_params = { \
1918 .dma_dev = NULL \
1919 }, \
1920 .async.rx_dma_params = { \
1921 .dma_dev = NULL \
1922 }, \
1923
1924 #define DEV_DATA_ASYNC(n) \
1925 COND_CODE_0(DT_INST_PROP(n, io_mapped), \
1926 (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
1927 (DMA_PARAMS(n)), (DMA_PARAMS_NULL(n)))), \
1928 (DMA_PARAMS_NULL(n)))
1929 #else
1930 #define DEV_DATA_ASYNC(n)
1931 #endif /* CONFIG_UART_ASYNC_API */
1932
1933
1934 #define UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1935 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \
1936 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1937 .clock_dev = NULL, \
1938 .clock_subsys = NULL, \
1939 ), ( \
1940 .sys_clk_freq = 0, \
1941 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1942 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(\
1943 0, clocks, clkid), \
1944 ) \
1945 ) \
1946 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pcp), \
1947 (.pcp = DT_INST_PROP_OR(n, pcp, 0),)) \
1948 .reg_interval = (1 << DT_INST_PROP(n, reg_shift)), \
1949 IF_ENABLED(CONFIG_PINCTRL, \
1950 (.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),)) \
1951 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, resets), \
1952 (.reset_spec = RESET_DT_SPEC_INST_GET(n),))
1953
1954 #define UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1955 .uart_config.baudrate = DT_INST_PROP_OR(n, current_speed, 0), \
1956 .uart_config.parity = UART_CFG_PARITY_NONE, \
1957 .uart_config.stop_bits = UART_CFG_STOP_BITS_1, \
1958 .uart_config.data_bits = UART_CFG_DATA_BITS_8, \
1959 .uart_config.flow_ctrl = \
1960 COND_CODE_1(DT_INST_PROP_OR(n, hw_flow_control, 0), \
1961 (UART_CFG_FLOW_CTRL_RTS_CTS), \
1962 (UART_CFG_FLOW_CTRL_NONE)), \
1963 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, dlf), \
1964 (.dlf = DT_INST_PROP_OR(n, dlf, 0),)) \
1965 DEV_DATA_ASYNC(n) \
1966
1967 #define UART_NS16550_DEVICE_IO_MMIO_INIT(n) \
1968 UART_NS16550_IRQ_FUNC_DECLARE(n); \
1969 IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(n))); \
1970 static const struct uart_ns16550_dev_config uart_ns16550_dev_cfg_##n = { \
1971 COND_CODE_1(DT_INST_PROP_OR(n, io_mapped, 0), \
1972 (.port = DT_INST_REG_ADDR(n),), \
1973 (DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),)) \
1974 IF_ENABLED(DT_INST_PROP_OR(n, io_mapped, 0), \
1975 (.io_map = true,)) \
1976 UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1977 DEV_CONFIG_IRQ_FUNC_INIT(n) \
1978 }; \
1979 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1980 UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1981 }; \
1982 DEVICE_DT_INST_DEFINE(n, uart_ns16550_init, NULL, \
1983 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
1984 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
1985 &uart_ns16550_driver_api); \
1986 UART_NS16550_IRQ_FUNC_DEFINE(n)
1987
1988 #define UART_NS16550_DEVICE_PCIE_INIT(n) \
1989 UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n); \
1990 DEVICE_PCIE_INST_DECLARE(n); \
1991 IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(n))); \
1992 static const struct uart_ns16550_dev_config uart_ns16550_dev_cfg_##n = { \
1993 UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1994 DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n) \
1995 DEVICE_PCIE_INST_INIT(n, pcie) \
1996 }; \
1997 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1998 UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1999 }; \
2000 DEVICE_DT_INST_DEFINE(n, uart_ns16550_init, NULL, \
2001 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
2002 PRE_KERNEL_1, \
2003 CONFIG_SERIAL_INIT_PRIORITY, \
2004 &uart_ns16550_driver_api); \
2005 UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n)
2006
2007 #define UART_NS16550_DEVICE_INIT(n) \
2008 COND_CODE_1(DT_INST_ON_BUS(n, pcie), \
2009 (UART_NS16550_DEVICE_PCIE_INIT(n)), \
2010 (UART_NS16550_DEVICE_IO_MMIO_INIT(n)))
2011
2012 DT_INST_FOREACH_STATUS_OKAY(UART_NS16550_DEVICE_INIT)
2013
