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Searched defs:ICACHE0_BASE (Results 1 – 25 of 109) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21a010f512im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21a010f768im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21a020f1024im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21a020f512im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21a020f768im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21b010f1024im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21b010f512im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21b010f768im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21b020f1024im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21b020f512im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32mg21b020f768im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Drm21z000f1024im32.h604 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
606 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512gn32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c224f512im32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22e224f512im40.h642 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
644 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c112f352gm32.h626 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
628 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c224f512im40.h642 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
644 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22e224f512im32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c112f352gm40.h640 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
642 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c222f352gm32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c222f352gm40.h642 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
644 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c222f352gn32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c224f512gm32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
Defr32bg22c224f512gm40.h642 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
644 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro

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