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Searched defs:HFXO0_BASE (Results 1 – 21 of 21) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21a010f512im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21a010f768im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21a020f1024im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21a020f512im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21a020f768im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21b010f1024im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21b010f768im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21b020f1024im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21b010f512im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21b020f512im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg21b020f768im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Drm21z000f1024im32.h564 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
566 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512im40.h602 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
604 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27c230f768im32.h636 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
638 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32bg27c140f768im32.h641 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
643 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32bg27c320f768gj39.h642 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
644 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32bg27c230f768im40.h656 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
658 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32bg27c140f768im40.h657 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
659 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24b310f1536im48.h866 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
868 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
Defr32mg24b220f1536im48.h858 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
860 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro