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Searched defs:FCR (Results 1 – 25 of 91) sorted by relevance

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/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
DS32K142_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K144_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K146_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K144W_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K116_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K118_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K142W_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
DS32K148_LPSPI.h88 …__IO uint32_t FCR; /**< The FIFO Control register contains the RXWAT… member
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h93 __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ member
DS32K344_MU.h85 __IO uint32_t FCR; /**< Flag Control Register, offset: 0x100 */ member
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CTU.h96 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x70 */ member
DS32Z2_MU.h85 __IO uint32_t FCR; /**< Flag Control Register, offset: 0x100 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h4910 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h4909 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h8870 __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ member
10499 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
DK32L3A60_cm4.h9505 __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ member
11134 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h7897 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h4908 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h7899 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h7901 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7475 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7473 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h10081 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h11080 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h11085 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member

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