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Searched defs:DMA_CTR1_DDW_LOG2_1 (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2283 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32wba54xx.h3051 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32wba52xx.h2868 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32wba5mxx.h3051 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32wba55xx.h3051 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3886 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h523xx.h5245 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h533xx.h5654 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h562xx.h5688 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h573xx.h8181 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h563xx.h7772 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6336 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u535xx.h5936 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u575xx.h6335 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u585xx.h6784 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u595xx.h6591 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u5a5xx.h7040 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u5f7xx.h6887 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u599xx.h6879 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u5g7xx.h7336 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32u5f9xx.h7007 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7s7xx.h5564 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h7s3xx.h5485 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h7r3xx.h5040 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro
Dstm32h7r7xx.h5117 #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ macro

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