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Searched defs:DIGTMP_TER_TPE4_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h11709 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h11679 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h13993 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
DMCXN546_cm33_core1.h13993 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h13993 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
DMCXN547_cm33_core1.h13993 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h14039 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
DMCXN947_cm33_core0.h14039 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h14039 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro
DMCXN946_cm33_core1.h14039 #define DIGTMP_TER_TPE4_MASK (0x100000U) macro