1 /***************************************************************************//**
2 * \file cy_sd_host.h
3 * \version 2.1
4 *
5 * This file provides constants and parameter values for
6 * the SD Host Controller driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2021 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_sd_host
28 * \{
29 * This driver provides the user an easy method for accessing standard
30 * Host Controller Interface (HCI) registers and provides some simple
31 * functionality on top of the HCI for reading and writing data to
32 * an SD card, eMMc card or a SDIO device.
33 *
34 * The functions and other declarations used in this driver are in cy_sd_host.h.
35 * You can include cy_pdl.h to get access to all functions
36 * and declarations in the PDL.
37 *
38 * Features:
39 * * Supports data transfer using CPU, SDMA, ADMA2 and ADMA3 modes
40 * * Supports a configurable block size (1 to 65,535 Bytes)
41 * * Supports interrupt enabling and masking
42 * * Supports SD-HCI Host version 4 mode or less
43 * * Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
44 * * SD interface features:
45 * * - Supports the 4-bit interface
46 * * - Supports Ultra High Speed (UHS-I) mode
47 * * - Supports Default Speed (DS), High Speed (HS), SDR12, SDR25, SDR50, and DDR50 speed modes
48 * * - Supports SDIO card interrupts in both 1-bit and 4-bit modes
49 * * - Supports Standard capacity (SDSC), High capacity (SDHC)
50 * and Extended capacity (SDXC) memory
51 * * - Supports CRC and check for command and data packets
52 * * - Supports packet timeouts
53 * * - Handles the SDIO card interrupt
54 * * eMMC interface features:
55 * * - Supports 1-bit/4-bit/8-bit interfaces
56 * * - Supports legacy and High Speed SDR speed modes
57 * * - Supports CRC and check for command and data packets
58 * * - Supports packet timeouts
59 *
60 * Unsupported Features:
61 * * Wrap address transfers
62 * * eMMC boot operation
63 * * Suspend/Resume operation in an SDIO card
64 * * Operation in SDR104, UHS-II mode, HS200, and HS400
65 * * Serial Peripheral Interface (SPI) protocol mode
66 * * Interrupt input pins for the embedded SD system
67 * * Auto-tuning
68 * * Command queuing
69 *
70 * The SD, eMMC, and SDIO cards have the similar physical interface:
71 * clock, command line, and data lines.
72 * The SD card is removable and requires the SD card connector to connect
73 * to the PSoC device. This connector also has the card_mech_write_prot switch
74 * for mechanical write protection and the card_detect_n switch for card detection.
75 * The eMMC card also has DAT4-DAT7 pins for 8-bit mode and the EMMC_RESET pin.
76 * \image html sd_card_connector.png
77 * The driver has a low-level and high-level APIs.
78 * The low-level functions provide an easy method to read and write registers.
79 * Also, these functions allow valid interaction with an SD Card, eMMC card,
80 * and SDIO card.
81 * The high-level functions provide an easy mechanism to enumerate a device,
82 * read, write, and erase data. They are RTOS-friendly.
83 * When starting a command, these functions do not wait until the command completes.
84 * The interrupt and flags are used to check when the transfer completes.
85 * This allows to put RTOS delays in the user code.
86 *
87 * \section group_sd_host_section_Configuration_Considerations Configuration Considerations
88 * The SD Host driver configuration can be divided to a number of sequential
89 * steps listed below:
90 * * \ref group_sd_host_enable
91 * * \ref group_sd_host_pins
92 * * \ref group_sd_host_clock
93 * * \ref group_sd_host_intr
94 * * \ref group_sd_host_config
95 * * \ref group_sd_host_card_init
96 *
97 * \note
98 * The SD Host driver is built on top of the SDHC hardware block. The SDHC1 instance is
99 * used as an example for all code snippets. Modify the code to match your
100 * design.
101 *
102 * \subsection group_sd_host_enable Enable SD Host
103 * Enable the SDHC block calling \ref Cy_SD_Host_Enable.
104 *
105 * \subsection group_sd_host_pins Assign and Configure Pins
106 * Only dedicated SD Host pins can be used for SD Host operation. The HSIOM
107 * register must be configured to connect the block to the pins. Also, the SD Host
108 * pins must be configured in Strong Drive, Input buffer on:
109 *
110 * \snippet sd_host/snippet/main.c SD_HOST_CFG_PINS
111 *
112 * \subsection group_sd_host_clock Assign Clock Source
113 * The SD Host is sourced from the CLK_HF clock. The clock must be set to 100 MHz:
114 *
115 * \snippet sd_host/snippet/main.c SD_HOST_CFG_ASSIGN_CLOCK
116 *
117 * \subsection group_sd_host_intr Configure Interrupt (Optional)
118 * The user can set up the interrupt for SD Host operation.
119 * The user is responsible for writing its own Interrupt handler.
120 * The Interrupt must be called in the interrupt handler for the selected SDHC
121 * instance. Also this interrupt must be enabled in the NVIC otherwise
122 * it will not work.
123 * It is the user's responsibility to clear the normal and error interrupt statuses.
124 * The interrupt statuses can be read using \ref Cy_SD_Host_GetNormalInterruptStatus
125 * and \ref Cy_SD_Host_GetErrorInterruptStatus.
126 * To clear the interrupt statuses, use \ref Cy_SD_Host_ClearNormalInterruptStatus
127 * and \ref Cy_SD_Host_ClearErrorInterruptStatus.
128 *
129 * \snippet sd_host/snippet/main.c SD_HOST_INTR_A
130 * \snippet sd_host/snippet/main.c SD_HOST_INTR_B
131 *
132 * \subsection group_sd_host_config Configure SD Host
133 * To set up the SD Host driver, provide the configuration parameters in the
134 * \ref cy_stc_sd_host_init_config_t structure. Set the emmc parameter to true for
135 * the eMMC-device, otherwise set it to false. Set dmaType if DMA mode
136 * is used for read/write operations. The other parameters are optional for
137 * operation. To initialize the driver, call the \ref Cy_SD_Host_Init
138 * function providing a pointer to the filled \ref cy_stc_sd_host_init_config_t
139 * structure and allocated \ref cy_stc_sd_host_context_t.
140 *
141 * \snippet sd_host/snippet/main.c SD_HOST_CONTEXT
142 * \snippet sd_host/snippet/main.c SD_HOST_CFG
143 *
144 * The SD, eMMC or SDIO card can be configured using the \ref Cy_SD_Host_InitCard
145 * function as a pointer to the filled \ref cy_stc_sd_host_sd_card_config_t
146 * structure and allocated \ref cy_stc_sd_host_context_t.
147 *
148 * \subsection group_sd_host_card_init Initialize the card
149 * Finally, enable the card operation calling
150 * \ref Cy_SD_Host_InitCard.
151 *
152 * \snippet sd_host/snippet/main.c SD_HOST_ENABLE_CARD_INIT
153 *
154 * \section group_sd_host_use_cases Common Use Cases
155 *
156 * \subsection group_sd_host_sd_card_mode SD card Operation
157 * The master API is divided into two categories:
158 * \ref group_sd_host_high_level_functions and
159 * \ref group_sd_host_low_level_functions. Therefore, there are two
160 * methods for initiating SD card transactions using either <b>Low-Level</b> or
161 * <b>High-Level</b> API.
162 *
163 * \subsubsection group_sd_host_master_hl Use High-Level Functions
164 * Call \ref Cy_SD_Host_Read or \ref Cy_SD_Host_Write to
165 * communicate with the SD memory device. These functions do not block
166 * in DMA mode and only start a transaction. After a transaction starts,
167 * the user should check the further data-transaction complete event.
168 * The example below shows sending and reading data in DMA mode.
169 *
170 * \snippet sd_host/snippet/main.c SD_HOST_WRITE_READ_ADMA2
171 *
172 * \subsubsection group_sd_host_master_ll Use Low-Level Functions
173 * Call \ref Cy_SD_Host_InitDataTransfer to initialize the SD block
174 * for a data transfer. It does not start a transfer. To start a transfer
175 * call \ref Cy_SD_Host_SendCommand after calling this function.
176 * If DMA is not used for Data transfer then the buffer needs to be filled
177 * with data first if this is a write.
178 * Wait the transfer complete event.
179 * ADMA3 mode requires calling \ref Cy_SD_Host_InitDataTransfer to
180 * initialize the DMA transaction. The ADMA3 mode example is shown below.
181 *
182 * \snippet sd_host/snippet/main.c SD_HOST_WRITE_READ_ADMA3
183 *
184 * \subsection group_sd_host_emmc_card_mode eMMC Card Operation
185 * eMMC cards use the same API for writing and reading data.
186 * Additionally, eMMC requires configuring GPIO pins for DAT signals
187 * in 8-bit mode and card_emmc_reset_n pin if needed.
188 * The emmc member of \ref cy_stc_sd_host_init_config_t structure must
189 * be set to "true".
190 *
191 * \subsection group_sd_host_sdio_combo_card_mode eMMC SDIO or Combo Card Operation
192 * \ref Cy_SD_Host_InitCard() initializes all types of cards and
193 * automatically detects the card type: SD, SDIO or Combo card.
194 * SDIO cards have their input-output (I/O) functions that can be
195 * controlled using the GPIO driver.
196 * Combo Cards can use both I/O and memory API.
197 *
198 * \section group_sd_host_lp Low Power Support
199 * The SD Host does not operate in Hibernate and Deep Sleep modes but it
200 * can automatically continue write/read operation after restoring from
201 * Deep Sleep mode. SD CLK must be disabled before going to Deep Sleep mode
202 * and can be enabled after wake up from Deep Sleep mode.
203 * To reduce the power consumption in Active mode, the user can stop
204 * the clock of the SD bus but the following interrupts can be allowed:
205 * Card Insert, Card Removal and SDIO Interrupt.
206 *
207 * \section group_sd_host_remove_insert SD Card Removal and Insertion
208 * SD card removal or insertion can be detected by calling
209 * \ref Cy_SD_Host_GetNormalInterruptStatus which returns
210 * the card removal or card insertion events
211 * (CY_SD_HOST_CARD_REMOVAL or CY_SD_HOST_CARD_INSERTION bits).
212 * These events should be reset using
213 * \ref Cy_SD_Host_ClearNormalInterruptStatus when they occur.
214 * When the card is removed, the SDHC block disables the CMD/DAT output.
215 * It is recommended to set DAT pins to
216 * the Digital High-Z (CY_GPIO_DM_HIGHZ) drive mode when
217 * card removal is detected. This can be doing using the GPIO driver.
218 * When the card is inserted, the SDHC block automatically disables
219 * the card power and clock. After card insertion,
220 * the user should set the DAT pins drive mode back to Strong Drive,
221 * Input buffer on (CY_GPIO_DM_STRONG), and then call \ref Cy_SD_Host_InitCard.
222 * \note If CARD_INTERRUPT is enabled and DAT pins are not set to
223 * Digital High-Z drive mode then the interrupt will continuously
224 * trigger because the DAT1 line is driven low upon card re-insertion.
225 * The user will have to detect the card removal in the ISR handler,
226 * apply the power to the card using \ref Cy_SD_Host_EnableCardVoltage,
227 * set to the DAT pins drive mode to the Digital High-Z (CY_GPIO_DM_HIGHZ)
228 * and clear CY_SD_HOST_CARD_INTERRUPT bit
229 * using \ref Cy_SD_Host_ClearNormalInterruptStatus.
230 *
231 * \section group_sd_host_low_voltage_signaling Low Voltage Signaling
232 * When lowVoltageSignaling is true, the SD Host driver sets UHS-I mode
233 * during the card initialization. The SD Host driver always starts talking
234 * to the card at 3.3V and then later switches to 1.8V. There is no internal
235 * regulator in the PSoC 6 to change SD signals from 3.3V to 1.8V.
236 * Thus, an external regulator is needed for the VDDIO of the PSoC device
237 * to provide the ability to go from 3.3V to 1.8V.
238 * The SD Host driver sets the io_volt_sel pin to high which is used to
239 * control the external regulator.
240 * \image html sd_host_low_voltage_signaling.png
241 *
242 * \section group_sd_host_more_information More Information
243 *
244 * Refer to the appropriate device technical reference manual (TRM) for
245 * a detailed description of the registers.
246 *
247 * \section group_sd_host_Changelog Changelog
248 * <table class="doxtable">
249 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
250 * <tr>
251 * <td> 2.1</td>
252 * <td>Updated the behaviour of \ref Cy_SD_Host_AbortTransfer function to check the R1B response. Minor documentation updates.</td>
253 * <td>Defect fixing. Documentation enhancement.</td>
254 * </tr>
255 * <tr>
256 * <td> 2.0</td>
257 * <td>Added support for DDR50 mode and modified Cy_SD_Host_InitCard() API
258 * to set highest possible bus speed mode. Minor documentation updates.</td>
259 * <td>New feature implementation and documentation enhancement.</td>
260 * </tr>
261 * <tr>
262 * <td> 1.90</td>
263 * <td>Fixed the Cy_SD_Host_SoftwareReset() function behaviour.
264 * Now it waits until corresponding reset bit gets cleared by SDHC IP block.</td>
265 * <td>Defect fixing.</td>
266 * </tr>
267 * <tr>
268 * <td> 1.80</td>
269 * <td>Added an internal function.</td>
270 * <td>Code efficiency enhancement.</td>
271 * </tr>
272 * <tr>
273 * <td>1.70</td>
274 * <td>Allow SDIO Card initialization through Cy_SD_Host_InitCard() API.
275 * Added new API Cy_SD_Host_GetBlockCount().
276 * </td>
277 * <td>Code enhancement, minor defect fixing.</td>
278 * </tr>
279 * <tr>
280 * <td>1.60</td>
281 * <td>Fixed/Documented MISRA 2012 violations.</td>
282 * <td>MISRA 2012 compliance.</td>
283 * </tr>
284 * <tr>
285 * <td>1.50.1</td>
286 * <td>Minor documentation updates.</td>
287 * <td>Documentation enhancement.</td>
288 * </tr>
289 * <tr>
290 * <td>1.50</td>
291 * <td>The default value of the SD-clock rump-up time during a wakeup
292 * from Deep Sleep is reduced to 1 us, for details,
293 * see \ref Cy_SD_Host_DeepSleepCallback description.</td>
294 * <td>Optimization for cases of specific wakeup timing requirements.</td>
295 * </tr>
296 * <tr>
297 * <td>1.40</td>
298 * <td>Added a possibility to
299 * customize the SD-clock rump-up time during a wakeup from Deep Sleep,
300 * for details, see \ref Cy_SD_Host_DeepSleepCallback description.</td>
301 * <td>Workaround for cases of specific wakeup timing requirements.</td>
302 * </tr>
303 * <tr>
304 * <td>1.30</td>
305 * <td>The internal function implementation is changed.</td>
306 * <td>Code efficiency enhancement, minor defect fixing.</td>
307 * </tr>
308 * <tr>
309 * <td rowspan="2"> 1.20</td>
310 * <td>Added the Cy_SD_Host_DeepSleepCallback() function.</td>
311 * <td>Driver maintenance.</td>
312 * </tr>
313 * <tr>
314 * <td>Fixed the Cy_SD_Host_GetCsd() function behaviour.
315 * Now the cy_stc_sd_host_context_t::maxSectorNum is being updated correctly</td>
316 * <td>Defect fixing.</td>
317 * </tr>
318 * <tr>
319 * <td> 1.10.1</td>
320 * <td>Documentation of the MISRA rule violation.</td>
321 * <td>MISRA compliance.</td>
322 * </tr>
323 * <tr>
324 * <td>1.10</td>
325 * <td>The PLL and CLK disable sequence in \ref Cy_SD_Host_DisableSdClk()
326 * is changed to disable CLK first.<br>
327 * The Low-Power Support section is updated with additional
328 * information about disabling CLK.<br>
329 * The context initialization in \ref Cy_SD_Host_Init() is corrected.<br>
330 * Updated the Write/Read sequence in \ref Cy_SD_Host_Read() and
331 * \ref Cy_SD_Host_Write()functions for non DMA mode.<br>
332 * </td>
333 * <td>Defect fixing.</td>
334 * </tr>
335 * <tr>
336 * <td>1.0</td>
337 * <td>The initial version.</td>
338 * <td></td>
339 * </tr>
340 * </table>
341 *
342 * \defgroup group_sd_host_macros Macros
343 * \{
344 * \defgroup group_sd_host_macros_general_purpose General Purpose Macros
345 * \defgroup group_sd_host_macros_card_states Card States
346 * \{
347 * The masks below can be used to check the CURRENT_STATE bitfield
348 * of the \ref Cy_SD_Host_GetCardStatus function return value.
349 * \}
350 * \defgroup group_sd_host_macros_card_status Card Status (CMD13) Bits
351 * \{
352 * The masks below can be used with the
353 * \ref Cy_SD_Host_GetCardStatus function.
354 * \}
355 * \defgroup group_sd_host_macros_scr SCR Register Masks
356 * \{
357 * The masks below can be used with the
358 * \ref Cy_SD_Host_GetScr function.
359 * \}
360 * \defgroup group_sd_host_macros_cid CID Register Masks
361 * \{
362 * The masks below can be used with the
363 * \ref Cy_SD_Host_GetCid function.
364 * \}
365 * \defgroup group_sd_host_macros_csd CSD Register Masks
366 * \{
367 * The masks below are for CSD Register Version 2.0 and can be
368 * used with the \ref Cy_SD_Host_GetCsd function.
369 * \}
370 * \defgroup group_sd_host_macros_events SD Host Events
371 * \{
372 * The constants below can be used with
373 * \ref Cy_SD_Host_GetNormalInterruptStatus,
374 * \ref Cy_SD_Host_ClearNormalInterruptStatus,
375 * \ref Cy_SD_Host_GetErrorInterruptStatus and
376 * \ref Cy_SD_Host_ClearErrorInterruptStatus functions.
377 * Each event is encoded in a separate bit, and therefore it is possible to
378 * notify about multiple events.
379 * \}
380 * \defgroup group_sd_host_macros_present_status SD Host Present Status
381 * \{
382 * The constants below can be used with the
383 * \ref Cy_SD_Host_GetPresentState function.
384 * Each status is encoded in a separate bit, and therefore it is possible to
385 * notify about multiple statuses.
386 * \}
387 * \}
388 * \defgroup group_sd_host_functions Functions
389 * \{
390 * \defgroup group_sd_host_high_level_functions High-Level
391 * \defgroup group_sd_host_low_level_functions Low-Level
392 * \defgroup group_sd_host_interrupt_functions Interrupt
393 * \}
394 * \defgroup group_sd_host_data_structures Data Structures
395 * \defgroup group_sd_host_enums Enumerated Types
396 */
397
398 #ifndef CY_SD_HOST_PDL_H
399 #define CY_SD_HOST_PDL_H
400
401 #include "cy_device.h"
402
403 #if defined (CY_IP_MXSDHC)
404
405 #include <stdbool.h>
406 #include <stddef.h>
407 #include "cy_syslib.h"
408 #include "cy_syspm.h"
409
410 #if defined (__CC_ARM)
411 #pragma anon_unions
412 #endif
413
414 /* C binding of definitions if building with C++ compiler */
415 #ifdef __cplusplus
416 extern "C"
417 {
418 #endif
419
420 /**
421 * \addtogroup group_sd_host_macros_general_purpose
422 * \{
423 */
424
425 /** Driver major version */
426 #define CY_SD_HOST_DRV_VERSION_MAJOR 2
427
428 /** Driver minor version */
429 #define CY_SD_HOST_DRV_VERSION_MINOR 1
430
431 /******************************************************************************
432 * API Constants
433 ******************************************************************************/
434
435 #define CY_SD_HOST_ID CY_PDL_DRV_ID(0x3AU) /**< SD_HOST PDL ID */
436
437 #define CY_SD_HOST_BLOCK_SIZE (512UL) /**< The SD memory card block size. */
438
439 #define CY_SD_HOST_SDSC_ADDR_SHIFT (9U) /**< This constant is used to get the
440 * address for the SDSC card using the
441 * shift operation instead of multiply to 512.
442 */
443
444 /* SD output clock. */
445 #define CY_SD_HOST_CLK_25M (25UL * 1000UL * 1000UL) /**< Clk = 25 MHz. */
446 #define CY_SD_HOST_CLK_50M (50UL * 1000UL * 1000UL) /**< Clk = 50 MHz. */
447 #define CY_SD_HOST_CLK_100M (100UL * 1000UL * 1000UL) /**< Clk = 100 MHz. */
448
449 #define CY_SD_HOST_CLK_RAMP_UP_TIME_MS (100UL) /**< The host power ramp up time. */
450
451 #ifndef CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP /* Define of the CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP
452 * suppresses CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP
453 */
454 #ifndef CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP /*
455 * This is legacy constant.
456 * It is left here just for backward compatibility.
457 * Do not use it in new designs.
458 */
459 #define CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP (1U) /**< The default host power ramp up time during wake up from deep sleep. */
460 #else
461 #define CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP (CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP * 1000U)
462 #endif /* !defined CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP */
463 #endif /* !defined CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP */
464
465 /* ADMA constants. */
466 #define CY_SD_HOST_ADMA_NOP (0x0UL) /**< Does not execute the current line and go to next line. */
467 #define CY_SD_HOST_ADMA_RSV (0x2UL) /**< Reserved. */
468 #define CY_SD_HOST_ADMA_TRAN (0x4UL) /**< Transfers data of one descriptor line. */
469 #define CY_SD_HOST_ADMA_LINK (0x6UL) /**< The link to another descriptor. */
470 #define CY_SD_HOST_ADMA3_CMD (0x1UL) /**< The Command descriptor. */
471 #define CY_SD_HOST_ADMA3_INTERGRATED (0x7UL) /**< The Integrated descriptor. */
472 #define CY_SD_HOST_ADMA2_DESCR_SIZE (0x2UL) /**< The ADMA2 descriptor size. */
473
474 /* ADMA descriptor table positions. */
475 #define CY_SD_HOST_ADMA_ATTR_VALID_POS (0U) /**< The ADMA Attr Valid position. */
476 #define CY_SD_HOST_ADMA_ATTR_END_POS (1U) /**< The ADMA Attr End position. */
477 #define CY_SD_HOST_ADMA_ATTR_INT_POS (2U) /**< The ADMA Attr Int position. */
478 #define CY_SD_HOST_ADMA_ACT_POS (3U) /**< The ADMA Act position. */
479 #define CY_SD_HOST_ADMA_RESERVED2_POS (6U) /**< The ADMA Reserved2 position. */
480 #define CY_SD_HOST_ADMA_LEN_POS (16U) /**< The ADMA Len position. */
481
482 /** \cond INTERNAL_MACROS */
483
484 #define CY_SD_HOST_EMMC_T_RSTW_US (1U)
485 #define CY_SD_HOST_EMMC_T_RSCA_US (200U)
486 #define CY_SD_HOST_INIT_CLK_FREQUENCY_KHZ (400U) /* The CLK frequency in kHz during card initialization. */
487 #define CY_SD_HOST_3_PERIODS_US (((1000U * 3U) / CY_SD_HOST_INIT_CLK_FREQUENCY_KHZ) + 1U)
488
489 /** \endcond */
490
491 /** \} group_sd_host_macros_general_purpose */
492
493 /**
494 * \addtogroup group_sd_host_macros_card_states
495 * \{
496 */
497
498 #define CY_SD_HOST_CARD_IDLE (0x0UL) /**< The card idle state. */
499 #define CY_SD_HOST_CARD_READY (0x1UL) /**< The card ready state. */
500 #define CY_SD_HOST_CARD_IDENT (0x2UL) /**< The card identification state. */
501 #define CY_SD_HOST_CARD_STBY (0x3UL) /**< The card stand-by state. */
502 #define CY_SD_HOST_CARD_TRAN (0x4UL) /**< The card transition state. */
503 #define CY_SD_HOST_CARD_DATA (0x5UL) /**< The card sending-data state. */
504 #define CY_SD_HOST_CARD_RCV (0x6UL) /**< The card receive-data state. */
505 #define CY_SD_HOST_CARD_PRG (0x7UL) /**< The card programming state. */
506 #define CY_SD_HOST_CARD_DIS (0x8UL) /**< The card disconnect state. */
507
508 /** \} group_sd_host_macros_card_states */
509
510 /**
511 * \addtogroup group_sd_host_macros_card_status
512 * \{
513 */
514
515 #define CY_SD_HOST_CMD13_OUT_OF_RANGE (31U) /**< The command's argument is out of range. */
516 #define CY_SD_HOST_CMD13_ADDRESS_ERROR (30U) /**< The address does not match the block length. */
517 #define CY_SD_HOST_CMD13_BLOCK_LEN_ERROR (29U) /**< The block length is not allowed for this card. */
518 #define CY_SD_HOST_CMD13_ERASE_SEQ_ERROR (28U) /**< An error in the sequence of erase commands occurred. */
519 #define CY_SD_HOST_CMD13_ERASE_PARAM (27U) /**< An invalid selection of write blocks for erase occurred. */
520 #define CY_SD_HOST_CMD13_WP_VIOLATION (26U) /**< The host attempts to write to a protected block
521 * or to the permanent write-protected card.
522 */
523 #define CY_SD_HOST_CMD13_CARD_IS_LOCKED (25U) /**< The card is locked by the host. */
524 #define CY_SD_HOST_CMD13_LOCK_ULOCK_FAILED (24U) /**< A sequence or password error occurred
525 * has been detected in the lock/unlock card command.
526 */
527 #define CY_SD_HOST_CMD13_COM_CRC_ERROR (23U) /**< The CRC of the previous command failed. */
528 #define CY_SD_HOST_CMD13_ILLEGAL_COMMAND (22U) /**< The command is not legal for the card state. */
529 #define CY_SD_HOST_CMD13_CARD_ECC_FAILED (21U) /**< The card internal ECC failed. */
530 #define CY_SD_HOST_CMD13_CC_ERROR (20U) /**< An internal card-controller error. */
531 #define CY_SD_HOST_CMD13_ERROR (19U) /**< A general or unknown error occurred. */
532 #define CY_SD_HOST_CMD13_CSD_OVERWRITE (16U) /**< Can be either one of the following
533 * errors:
534 * - The read only section of the CSD
535 * does not match the card content.
536 * - An attempt to reverse the copy (set
537 * as original) or permanent WP
538 * (unprotected) bits was made.
539 */
540 #define CY_SD_HOST_CMD13_WP_ERASE_SKIP (15U) /**< Set when only partial address space
541 * was erased due to existing write protected blocks
542 * or a temporary or permanent write protected
543 * card was erased.
544 */
545 #define CY_SD_HOST_CMD13_CARD_ECC_DISABLED (14U) /**< The command has been executed
546 * without using the internal ECC.
547 */
548 #define CY_SD_HOST_CMD13_CURRENT_STATE (9U) /**< The state of the card. */
549 #define CY_SD_HOST_CMD13_READY_FOR_DATA (8U) /**< The buffer is empty on the bus. */
550 #define CY_SD_HOST_CMD13_APP_CMD (5U) /**< The card will expect ACMD, or an
551 * indication that the command has
552 * been interpreted as ACMD.
553 */
554 #define CY_SD_HOST_CMD13_AKE_SEQ_ERROR (3U) /**< Error in the sequence of the
555 * authentication process.
556 */
557
558 #define CY_SD_HOST_CMD13_CURRENT_STATE_MSK (0x00001E00UL) /**< The current state mask of the card. */
559
560 /** \} group_sd_host_macros_card_status */
561
562 /**
563 * \addtogroup group_sd_host_macros_scr
564 * \{
565 */
566
567 #define CY_SD_HOST_SCR_SCR_STRUCTURE (0x000000F0UL) /**< Version number of the related SCR structure
568 * in the SD Memory Card Physical Layer Specification.
569 */
570
571 #define CY_SD_HOST_SCR_SD_SPEC (0x0000000FUL) /**< Describes the SD Memory Card Physical Layer
572 * Specification version supported by this card.
573 */
574
575 #define CY_SD_HOST_SCR_DATA_STAT_AFTER_ERASE (0x00008000UL) /**< Defines the data status after erase,
576 * whether it is '0' or '1' (the status is
577 * card vendor dependent).
578 */
579
580 #define CY_SD_HOST_SCR_SD_SECURITY (0x00007000UL) /**< Describes the security algorithm
581 * supported by the card.
582 */
583
584 #define CY_SD_HOST_SCR_SD_BUS_WIDTHS (0x00000F00UL) /**< Describes all the DAT bus widths that
585 * are supported by this card.
586 */
587
588 /** \} group_sd_host_macros_scr */
589
590 /**
591 * \addtogroup group_sd_host_macros_cid
592 * \{
593 */
594
595 #define CY_SD_HOST_SCR_CID_MDT (0x00000FFFUL) /**< The manufacturing date is composed of
596 * two hexadecimal digits (contained in cid[0]),
597 * one is 8 bits representing the year(y) and the
598 * other is 4 bits representing the month (m).
599 * The "m" field [11:8] is the month code. 1 = January.
600 * The "y" field [19:12] is the year code. 0 = 2000.
601 * As an example, the binary value of the Date field
602 * for production date "April 2018" will be:
603 * 00010010 0100.
604 */
605
606 #define CY_SD_HOST_SCR_CID_PSN_LSB (0xFFFF0000UL) /**< The mask for LSB part of the Serial Number
607 * (contained in cid[0]). The Serial Number is
608 * 32 bits of binary number.
609 */
610
611 #define CY_SD_HOST_SCR_CID_PSN_MSB (0x0000FFFFUL) /**< The mask for MSB part of the Serial Number
612 * (contained in cid[1]). The Serial Number is
613 * 32 bits of binary number.
614 */
615
616 #define CY_SD_HOST_SCR_CID_PRV (0x00FF0000UL) /**< The product revision is composed of two
617 * Binary Coded Decimal (BCD) digits (contained in cid[1]),
618 * four bits each, representing an "n.m" revision number.
619 * The "n" is the most significant nibble and "m" is the
620 * least significant nibble.
621 * As an example, the PRV binary value field for product
622 * revision "6.2" will be: 0110 0010b.
623 */
624
625 #define CY_SD_HOST_SCR_CID_PNM_LSB (0xFF000000UL) /**< The mask for LSB part (the first 8 bits) of the
626 * product name (contained in cid[1]). The product
627 * name is a string, 5-character ASCII string.
628 * As an example, the PNM hex value field for product name
629 * "EB1QT" will be: 0x4542315154.
630 */
631
632 #define CY_SD_HOST_SCR_CID_PNM_MSB (0xFFFFFFFFUL) /**< The mask for MSB part (the last 32 bits) of the
633 * product name (contained in cid[2]). The product
634 * name is a string, 5-character ASCII string.
635 * As an example, the PNM hex value field for product name
636 * "EB1QT" will be: 0x4542315154.
637 */
638
639 #define CY_SD_HOST_SCR_CID_OID (0x0000FFFFUL) /**< The mask for the OID (contained in cid[3]).
640 * The OID is a 2-character ASCII string that
641 * identifies the card OEM and/or the card contents
642 * (when used as a distribution media either on ROM or
643 * FLASH cards). The OID number is controlled, defined,
644 * and allocated to a SD Memory Card manufacturer by
645 * the SD-3C, LLC. This procedure is established to ensure
646 * uniqueness of the CID register.
647 * As an example, the OID hex value field for the card OEM
648 * "SM" will be: 0x534D.
649 */
650
651 #define CY_SD_HOST_SCR_CID_MID (0x00FF0000UL) /**< The mask for the MID (contained in cid[3]).
652 * MID is a 8-bit binary number that identifies the
653 * card manufacturer. The MID number is controlled,
654 * defined, and allocated to a SD Memory Card manufacturer
655 * by the SD-3C, LLC. This procedure is established to
656 * ensure uniqueness of the CID register.
657 */
658
659 /** \} group_sd_host_macros_cid */
660
661 /**
662 * \addtogroup group_sd_host_macros_csd
663 * \{
664 */
665
666 #define CY_SD_HOST_CSD_V2_CSD_STRUCTURE (0x0000FF00UL) /**< CSD structure (contained in csd[3]) */
667
668 #define CY_SD_HOST_CSD_V2_TAAC (0x0000FF00UL) /**< The data read access-time (contained in csd[3]).
669 * This field is fixed to 0Eh, which indicates 1 ms.
670 */
671
672 #define CY_SD_HOST_CSD_V2_NSAC (0x000000FFUL) /**< The data read access-time in CLK cycles (NSAC*100)
673 * (contained in csd[3]).
674 * This field is fixed to 00h. NSAC should not
675 * be used to calculate time-out values
676 * for CSD Version 2.0.
677 */
678
679 #define CY_SD_HOST_CSD_V2_TRAN_SPEED (0xFF000000UL) /**< The max. data transfer rate (contained in csd[2]).
680 * Equals to 0x32 (25 MHz) or 0x5A (50 MHz).
681 */
682
683 #define CY_SD_HOST_CSD_V2_CCC (0x00FFF000UL) /**< The card command classes (contained in csd[2]).
684 * The card command class register CCC defines which
685 * command classes are supported by this card.
686 * A value of 1 in a CCC bit means that the
687 * corresponding command class is supported.
688 */
689
690 #define CY_SD_HOST_CSD_V2_READ_BL_LEN (0x00000F00UL) /**< The max. read data block length (contained in csd[2]).
691 * This field is fixed to 9h, which
692 * indicates READ_BL_LEN=512 Byte.
693 */
694
695 #define CY_SD_HOST_CSD_V2_READ_BL_PARTIAL (0x00000080UL) /**< The partial blocks for read allowed (contained in csd[2]).
696 * This field is fixed to 0, which indicates
697 * partial block read is inhibited and only unit
698 * of block access is allowed.
699 */
700
701 #define CY_SD_HOST_CSD_V2_WRITE_BLK_MISALIGN (0x00000040UL) /**< The write block misalignment (contained in csd[2]).
702 * This field is fixed to 0, which indicates
703 * write access crossing physical block boundaries
704 * is always disabled in High Capacity SD Memory Card.
705 */
706
707 #define CY_SD_HOST_CSD_V2_READ_BLK_MISALIGN (0x00000020UL) /**< The read block misalignment (contained in csd[2]).
708 * This field is fixed to 0, which indicates
709 * read access crossing physical block boundaries
710 * is always disabled in High Capacity SD Memory Card.
711 */
712
713 #define CY_SD_HOST_CSD_V2_DSR_IMP (0x00000010UL) /**< The DSR implemented (contained in csd[2]).
714 * Defines if the configurable driver stage is
715 * integrated on the card.
716 */
717
718 #define CY_SD_HOST_CSD_V2_C_SIZE_MASK (0x3FFFFF00UL) /**< The device size (contained in csd[1]).
719 * This parameter is used to calculate the
720 * user data area capacity in the SD memory card
721 * (not include the protected area).
722 * The user data area capacity is calculated
723 * from C_SIZE as follows:
724 * memory capacity = (C_SIZE+1) * 512K byte.
725 */
726
727 #define CY_SD_HOST_CSD_V2_ERASE_BLK_EN (0x00000040UL) /**< The erase single block enable (contained in csd[1]).
728 * This field is fixed to 1, which means the
729 * host can erase one or multiple units of 512 bytes.
730 */
731
732 #define CY_SD_HOST_CSD_V2_SECTOR_SIZE_MSB (0x0000003FUL) /**< The MSB of erase sector size (6 MSB bits contained in csd[1]).
733 * SECTOR_SIZE is fixed to 7Fh, which indicates 64 KBytes.
734 * This value does not relate to erase operation.
735 * Version 2.00 cards indicates memory boundary by
736 * AU size and this field should not be used.
737 */
738
739 #define CY_SD_HOST_CSD_V2_SECTOR_SIZE_LSB (0x80000000UL) /**< The LSB of erase sector size
740 * (1 LSB bit of SECTOR_SIZE contained in csd[0]).
741 */
742
743 #define CY_SD_HOST_CSD_V2_WP_GRP_SIZE (0x7F000000UL) /**< The write protect group size (contained in csd[0]).
744 * This field is fixed to 00h. The High Capacity
745 * SD Memory Card does not support write protected groups.
746 */
747
748 #define CY_SD_HOST_CSD_V2_WP_GRP_ENABLE (0x00800000UL) /**< The write protect group enable (contained in csd[0]).
749 * This field is fixed to 0. The High Capacity SD Memory
750 * Card does not support write protected groups.
751 */
752
753 #define CY_SD_HOST_CSD_V2_R2W_FACTOR (0x001C0000UL) /**< The write speed factor (contained in csd[0]).
754 * This field is fixed to 2h, which indicates 4 multiples.
755 */
756
757 #define CY_SD_HOST_CSD_V2_WRITE_BL_LEN (0x0003C000UL) /**< The max. write data block length (contained in csd[0]).
758 * This field is fixed to 9h, which indicates
759 * WRITE_BL_LEN=512 Byte.
760 */
761
762 #define CY_SD_HOST_CSD_V2_WRITE_BL_PARTIAL (0x00002000UL) /**< The partial blocks for write allowed (contained in csd[0]).
763 * This field is fixed to 0, which indicates partial
764 * block read is inhibited and only unit of block
765 * access is allowed.
766 */
767
768 #define CY_SD_HOST_CSD_V2_FILE_FORMAT_GRP (0x00000080UL) /**< The File format group (contained in csd[0]).
769 * This field is set to 0. Host should not use this field.
770 */
771
772 #define CY_SD_HOST_CSD_V2_COPY (0x00000040UL) /**< The copy flag (OTP) (contained in csd[0]).
773 * Defines if the contents is original (=0) or
774 * has been copied (=1). The COPY bit for OTP and MTP
775 * devices, sold to end consumers, is set to 1,
776 * which identifies the card contents as a copy.
777 * The COPY bit is a one time programmable bit.
778 */
779
780 #define CY_SD_HOST_CSD_V2_PERM_WRITE_PROTECT (0x00000020UL) /**< The permanent write protection (contained in csd[0]).
781 * Permanently protects the entire card content
782 * against overwriting or erasing (all write and erase
783 * commands for this card are permanently disabled).
784 * The default value is 0, i.e. not permanently write
785 * protected.
786 */
787
788 #define CY_SD_HOST_CSD_V2_TMP_WRITE_PROTECT (0x00000010UL) /**< The temporary write protection (contained in csd[0]).
789 * Temporarily protects the entire card content
790 * from being overwritten or erased (all write
791 * and erase commands for this card are temporarily
792 * disabled). This bit can be set and reset.
793 * The default value is 0, i.e. not write protected.
794 */
795
796 #define CY_SD_HOST_CSD_V2_FILE_FORMAT (0x0000000CUL) /**< The File format (contained in csd[0]).
797 * This field is set to 0. Host should not use this field.
798 */
799
800
801 /** \} group_sd_host_macros_csd */
802
803 /**
804 * \addtogroup group_sd_host_macros_events
805 * \{
806 */
807
808 /**
809 * Command complete. In SD/eMMC mode, this event is set
810 * after detecting the end bit of a response except for Auto CMD12 and Auto CMD23.
811 * This event is not generated when the Response Interrupt is disabled.
812 */
813 #define CY_SD_HOST_CMD_COMPLETE (0x0001U)
814
815 /**
816 * Transfer complete. This event is set when a read/write
817 * transfer and a command with the Busy Status are completed.
818 */
819 #define CY_SD_HOST_XFER_COMPLETE (0x0002U)
820
821 /**
822 * Block gap. This event is set when both read/write
823 * transactions are stopped at the block gap due to a
824 * Stop-at-Block-Gap Request.
825 */
826 #define CY_SD_HOST_BGAP (0x0004U)
827
828 /**
829 * DMA Interrupt. This event is set if the Host Controller
830 * detects a SDMA Buffer Boundary during a transfer.
831 * For ADMA, the Host controller generates this
832 * interrupt by setting the Int field in the
833 * descriptor table.
834 * This interrupt is not generated after a Transfer
835 * Complete.
836 */
837 #define CY_SD_HOST_DMA_INTERRUPT (0x0008U)
838
839 /**
840 * The Buffer Write is ready. This event is set if
841 * the Buffer Write Enable changes from 0 to 1.
842 */
843 #define CY_SD_HOST_BUF_WR_READY (0x0010U)
844
845 /**
846 * The Buffer Read is ready. This event is set if
847 * the Buffer Read Enable changes from 0 to 1.
848 */
849 #define CY_SD_HOST_BUF_RD_READY (0x0020U)
850
851 /**
852 * Card insertion. This event is set if
853 * the Card Inserted in the Present State
854 * register changes from 0 to 1.
855 */
856 #define CY_SD_HOST_CARD_INSERTION (0x0040U)
857
858 /**
859 * Card removal. This event is set if
860 * the Card Inserted in the Present State
861 * register changes from 1 to 0.
862 */
863 #define CY_SD_HOST_CARD_REMOVAL (0x0080U)
864
865 /**
866 * The Card interrupt. This event reflects the
867 * synchronized value of DAT[1] Interrupt Input for SD Mode
868 */
869 #define CY_SD_HOST_CARD_INTERRUPT (0x0100U)
870
871 /**
872 * FX event.
873 * This status is set when R[14] of the response register is set to 1
874 * and Response Type R1/R5 is set to 0 in the Transfer Mode
875 * register. This interrupt is used with the response check function.
876 */
877 #define CY_SD_HOST_FX_EVENT (0x2000U)
878
879 /**
880 * Command Queuing event.
881 * This status is set if a Command Queuing/Crypto related event
882 * has occurred in eMMC/SD mode.
883 */
884 #define CY_SD_HOST_CQE_EVENT (0x4000U)
885
886 /**
887 * Error Interrupt.
888 * If any of the bits in the Error Interrupt Status
889 * register are set, then this bit is set.
890 */
891 #define CY_SD_HOST_ERR_INTERRUPT (0x8000U)
892
893 /**
894 * Command timeout error. In SD/eMMC Mode,
895 * this event is set only if no response is returned
896 * within 64 SD clock cycles from the end bit of the
897 * command. If the Host Controller detects a CMD line conflict,
898 * along with Command CRC Error bit, this event is set to 1,
899 * without waiting for 64 SD/eMMC card clock cycles.
900 */
901 #define CY_SD_HOST_CMD_TOUT_ERR (0x0001U)
902
903 /**
904 * Command CRC error. A Command CRC Error is generated
905 * in SD/eMMC mode when:
906 * 1. A response is returned and the Command Timeout
907 * Error is set to 0 (indicating no timeout),
908 * this bit is set to 1 when detecting a CRC error
909 * in the command response.
910 * 2. The Host Controller detects a CMD line conflict by
911 * monitoring the CMD line when a command is issued. If
912 * the Host Controller drives the CMD line to level 1, but
913 * detects level 0 on the CMD line at the next SD clock
914 * edge, then the Host Controller aborts the command (stop
915 * driving CMD line) and sets this bit to 1. The Command
916 * Timeout Error is also set to 1 to distinguish a CMD line
917 * conflict.
918 */
919 #define CY_SD_HOST_CMD_CRC_ERR (0x0002U)
920
921 /**
922 * Command End Bit error.
923 * This bit is set after detecting that the end bit of a command
924 * response is 0 in SD/eMMC mode.
925 */
926 #define CY_SD_HOST_CMD_END_BIT_ERR (0x0004U)
927
928 /**
929 * Command Index error.
930 * This bit is set if a Command Index error occurs in the
931 * command response in SD/eMMC mode.
932 */
933 #define CY_SD_HOST_CMD_IDX_ERR (0x0008U)
934
935 /**
936 * Data Timeout error.
937 * This bit is set in SD/eMMC mode when detecting one of the
938 * following timeout conditions:
939 * * Busy timeout for R1b, R5b type
940 * * Busy timeout after Write CRC status
941 * * Write CRC Status timeout
942 * * Read Data timeout.
943 */
944 #define CY_SD_HOST_DATA_TOUT_ERR (0x0010U)
945
946 /**
947 * Data CRC error.
948 * This error occurs in SD/eMMC mode after detecting a CRC
949 * error while transferring read data that uses the DAT line,
950 * after detecting the Write CRC status having a value other
951 * than 010 or when writing a CRC status timeout.
952 */
953 #define CY_SD_HOST_DATA_CRC_ERR (0x0020U)
954
955 /**
956 * Data End Bit error.
957 * This error occurs in SD/eMMC mode either when detecting 0
958 * at the end bit position of read data that uses the DAT line or
959 * at the end bit position of the CRC status.
960 */
961 #define CY_SD_HOST_DATA_END_BIT_ERR (0x0040U)
962
963 /**
964 * Current Limit error.
965 * The SD Host driver does not support this function,
966 * this bit is always set to 0.
967 */
968 #define CY_SD_HOST_CUR_LMT_ERR (0x0080U)
969
970 /**
971 * Auto CMD error.
972 * This error status is used by Auto CMD12 and Auto CMD23 in
973 * SD/eMMC mode. This bit is set after detecting that any of
974 * the bits D00 to D05 in the Auto CMD Error Status register has
975 * changed from 0 to 1. D07 is effective in case for Auto CMD12.
976 * The Auto CMD Error Status register is valid while this bit is set to
977 * 1 and may be cleared by clearing this bit.
978 */
979 #define CY_SD_HOST_AUTO_CMD_ERR (0x0100U)
980
981 /**
982 * ADMA error.
983 * This bit is set when the Host Controller detects an error during
984 * an ADMA-based data transfer. The possible reasons for an error:
985 * * An error response is received from the System bus;
986 * * ADMA3, ADMA2 Descriptors are invalid;
987 * * CQE Task or Transfer descriptors are invalid.
988 * When an error occurs, the state of the ADMA is saved in the
989 * ADMA Error Status register.
990 */
991 #define CY_SD_HOST_ADMA_ERR (0x0200U)
992
993 /**
994 * Tuning error.
995 * The SD Host driver does not support this function.
996 */
997 #define CY_SD_HOST_TUNING_ERR (0x0400U)
998
999 /**
1000 * Response error.
1001 * Host Controller Version 4.00 supports the response error check
1002 * function to avoid overhead of the response error check by Host
1003 * Driver during DMA execution. If the Response Error Check
1004 * Enable is set to 1 in the Transfer Mode register, the Host
1005 * Controller checks R1 or R5 response. If an error is detected
1006 * in a response, this bit is set to 1. This is applicable in
1007 * SD/eMMC mode.
1008 */
1009 #define CY_SD_HOST_RESP_ERR (0x0800U)
1010
1011 /**
1012 * Boot Acknowledgement error.
1013 * This bit is set when there is a timeout for boot
1014 * acknowledgement or after detecting the boot ACK status having
1015 * a value other than 010. This is applicable only when boot
1016 * acknowledgement is expected in eMMC mode.
1017 */
1018 #define CY_SD_HOST_BOOT_ACK_ERR (0x1000U)
1019
1020 /** \} group_sd_host_macros_events */
1021
1022 /**
1023 * \addtogroup group_sd_host_macros_present_status
1024 * \{
1025 */
1026
1027 /**
1028 * Command Inhibit (CMD).
1029 * This bit indicates the following:
1030 * - SD/eMMC mode: If this bit is set to 0, it indicates that the
1031 * CMD line is not in use and the Host controller can issue
1032 * an SD/eMMC command using the CMD line. This bit is
1033 * set when the command register is written. This bit is
1034 * cleared when the command response is received. This bit
1035 * is not cleared by the response of auto CMD12/23 but
1036 * cleared by the response of the Read/Write command.
1037 */
1038 #define CY_SD_HOST_CMD_INHIBIT (0x00000001UL)
1039
1040 /**
1041 * Command Inhibit (DAT).
1042 * This bit is applicable for SD/eMMC mode and is generated if
1043 * either the DAT line active or Read transfer active is set to 1. If
1044 * this bit is set to 0, it indicates that the Host Controller can
1045 * issue subsequent SD/eMMC commands.
1046 */
1047 #define CY_SD_HOST_CMD_CMD_INHIBIT_DAT (0x00000002UL)
1048
1049 /**
1050 * DAT Line Active (SD/eMMC Mode only).
1051 * This bit indicates whether one of the DAT lines on the
1052 * SD/eMMC bus is in use.
1053 * For Read transactions, this bit indicates whether a
1054 * read transfer is executing on the SD/eMMC bus.
1055 * For Write transactions, this bit indicates whether a
1056 * write transfer is executing on the SD/eMMC bus.
1057 * For a command with the Busy status, this status indicates whether the
1058 * command executing busy is executing on an SD or eMMC
1059 * bus.
1060 */
1061 #define CY_SD_HOST_DAT_LINE_ACTIVE (0x00000004UL)
1062
1063 /**
1064 * DAT[7:4] Line Signal Level.
1065 * These bits are used to check the DAT line level to recover from
1066 * errors and for debugging. These bits reflect the value of the
1067 * sd_dat_in (upper nibble) signal.
1068 */
1069 #define CY_SD_HOST_DAT_7_4 (0x000000F0UL)
1070
1071 /**
1072 * Write Transfer Active
1073 * This status indicates whether the Write transfer is active for
1074 * SD/eMMC mode.
1075 */
1076 #define CY_SD_HOST_WR_XFER_ACTIVE (0x00000100UL)
1077
1078 /**
1079 * Read Transfer Active.
1080 * This bit indicates whether the Read transfer is active for
1081 * SD/eMMC mode.
1082 */
1083 #define CY_SD_HOST_RD_XFER_ACTIVE (0x00000200UL)
1084
1085 /**
1086 * Buffer Write Enable.
1087 * This bit is used for non-DMA transfers. This bit is set if space
1088 * is available for writing data.
1089 */
1090 #define CY_SD_HOST_BUF_WR_ENABLE (0x00000400UL)
1091
1092 /**
1093 * Buffer Read Enable.
1094 * This bit is used for non-DMA transfers. This bit is set if valid
1095 * data exists in the Host buffer.
1096 */
1097 #define CY_SD_HOST_BUF_RD_ENABLE (0x00000800UL)
1098
1099 /**
1100 * Card Inserted.
1101 * This bit indicates whether a card has been inserted. The
1102 * Host Controller debounces this signal so that the Host Driver
1103 * does not need to wait for the signal to stabilize.
1104 */
1105 #define CY_SD_HOST_CARD_INSERTED (0x00010000UL)
1106
1107 /**
1108 * Card Stable.
1109 * This bit indicates the stability of the Card Detect Pin Level. A
1110 * card is not detected if this bit is set to 1 and the value of the
1111 * CARD_INSERTED bit is 0.
1112 */
1113 #define CY_SD_HOST_CARD_STABLE (0x00020000UL)
1114
1115 /**
1116 * Card Detect Pin Level.
1117 * This bit reflects the inverse synchronized value of the
1118 * card_detect_n signal.
1119 */
1120 #define CY_SD_HOST_CARD_DETECT_PIN_LEVEL (0x00040000UL)
1121
1122 /**
1123 * Write Protect Switch Pin Level.
1124 * This bit is supported only for memory and combo cards. This
1125 * bit reflects the synchronized value of the card_write_prot
1126 * signal.
1127 */
1128 #define CY_SD_HOST_WR_PROTECT_SW_LVL (0x00080000UL)
1129
1130 /**
1131 * DAT[3:0] Line Signal Level.
1132 * This bit is used to check the DAT line level to recover from
1133 * errors and for debugging. These bits reflect the value of the
1134 * sd_dat_in (lower nibble) signal.
1135 */
1136 #define CY_SD_HOST_DAT_3_0 (0x00F00000UL)
1137
1138 /**
1139 * DAT[0] Line Signal Level.
1140 * This bit is used to check the DAT0 line level to check R1b
1141 * response. This bit reflects the value of the sd_dat_in[0]
1142 * signal.
1143 */
1144 #define CY_SD_HOST_DAT_0_Msk (0x00100000UL)
1145
1146 /**
1147 * Command-Line Signal Level.
1148 * This bit is used to check the CMD line level to recover from
1149 * errors and for debugging. These bits reflect the value of the
1150 * sd_cmd_in signal.
1151 */
1152 #define CY_SD_HOST_CMD_LINE_LVL (0x01000000UL)
1153
1154 /**
1155 * Host Regulator Voltage Stable.
1156 * This bit is used to check whether the host regulator voltage is
1157 * stable for switching the voltage of UHS-I mode. This bit
1158 * reflects the synchronized value of the host_reg_vol_stable
1159 * signal.
1160 */
1161 #define CY_SD_HOST_HOST_REG_VOL (0x02000000UL)
1162
1163 /**
1164 * Command Not Issued by Error.
1165 * This bit is set if a command cannot be issued after setting
1166 * the command register due to an error except an Auto
1167 * CMD12 error.
1168 */
1169 #define CY_SD_HOST_CMD_ISSU_ERR (0x08000000UL)
1170
1171 /**
1172 * Sub Command Status.
1173 * This bit is used to distinguish between a main command and
1174 * a sub command status.
1175 */
1176 #define CY_SD_HOST_SUB_CMD_STAT (0x10000000UL)
1177
1178 /**
1179 * In Dormant Status.
1180 * This bit indicates whether UHS-II lanes enter the Dormant state
1181 * in the UHS-II mode. For SD/eMMC mode, this bit always
1182 * returns 0.
1183 */
1184 #define CY_SD_HOST_IN_DORMANT_ST (0x20000000UL)
1185
1186 /**
1187 * Lane Synchronization.
1188 * This bit indicates whether a lane is synchronized in UHSII
1189 * mode. For SD/eMMC mode, this bit always returns 0.
1190 */
1191 #define CY_SD_HOST_LANE_SYNC (0x40000000UL)
1192
1193 /**
1194 * UHS-II Interface Detection.
1195 * This bit indicates whether a card supports the UHS-II
1196 * interface. For SD/eMMC mode, this bit always returns 0.
1197 */
1198 #define CY_SD_HOST_UHS2_IF_DETECT (0x80000000UL)
1199
1200 /** \} group_sd_host_macros_present_status */
1201
1202
1203 /**
1204 * \addtogroup group_sd_host_enums
1205 * \{
1206 */
1207
1208 /******************************************************************************
1209 * Enumerations
1210 *****************************************************************************/
1211
1212 /** SD command types. */
1213 typedef enum
1214 {
1215 CY_SD_HOST_CMD_NORMAL = 0U, /**< Other commands */
1216 CY_SD_HOST_CMD_SUSPEND = 1U, /**< CMD52 for writing "Bus Suspend" in CCCR */
1217 CY_SD_HOST_CMD_RESUME = 2U, /**< CMD52 for writing "Function Select" in CCCR */
1218 CY_SD_HOST_CMD_ABORT = 3U /**< CMD12, CMD52 for writing "I/O Abort" in CCCR */
1219 }cy_en_sd_host_cmd_type_t;
1220
1221 /** SD Host auto command enable selection. */
1222 typedef enum
1223 {
1224 CY_SD_HOST_AUTO_CMD_NONE = 0U, /**< Auto command disable. */
1225 CY_SD_HOST_AUTO_CMD_12 = 1U, /**< Auto command 12 enable. */
1226 CY_SD_HOST_AUTO_CMD_23 = 2U, /**< Auto command 23 enable. */
1227 CY_SD_HOST_AUTO_CMD_AUTO = 3U /**< Auto command Auto enable. */
1228 }cy_en_sd_host_auto_cmd_t;
1229
1230 /** SD Host reset types. */
1231 typedef enum
1232 {
1233 CY_SD_HOST_RESET_DATALINE = 0U, /**< Reset the data circuit only. */
1234 CY_SD_HOST_RESET_CMD_LINE = 1U, /**< Reset the command circuit only. */
1235 CY_SD_HOST_RESET_ALL = 2U /**< Reset the whole SD Host controller. */
1236 }cy_en_sd_host_reset_t;
1237
1238 /** SD Host error interrupt types. */
1239 typedef enum
1240 {
1241 CY_SD_HOST_ADMA_ST_STOP = 0U, /**< Stop DMA - The SYS_ADR register points to
1242 * a location next to the error descriptor.
1243 */
1244 CY_SD_HOST_ADMA_ST_FDS = 1U, /**< Fetch Descriptor - The SYS_ADR register
1245 * points to the error descriptor.
1246 */
1247 CY_SD_HOST_ADMA_ST_TFR = 3U, /**< Transfer Data - SYS_ADR register points
1248 * to a location next to the error descriptor.
1249 */
1250 CY_SD_HOST_ADMA_LEN_ERR = 4U /**< The ADMA Length Mismatch error. */
1251 }cy_en_sd_host_adma_error_t;
1252
1253 /** Auto CMD Status error codes. */
1254 typedef enum
1255 {
1256 CY_SD_HOST_AUTO_CMD12_NOT_EXEC = 0U, /**< Auto CMD12 Not Executed. */
1257 CY_SD_HOST_AUTO_CMD_TOUT_ERR = 1U, /**< Auto CMD Timeout Error. */
1258 CY_SD_HOST_AUTO_CMD_CRC_ERR = 2U, /**< Auto CMD CRC Error. */
1259 CY_SD_HOST_AUTO_CMD_EBIT_ERR = 3U, /**< Auto CMD End Bit Error. */
1260 CY_SD_HOST_AUTO_CMD_IDX_ERR = 4U, /**< Auto CMD Index Error. */
1261 CY_SD_HOST_AUTO_CMD_RESP_ERR = 5U, /**< Auto CMD Response Error. */
1262 CY_SD_HOST_CMD_NOT_ISSUED_AUTO_CMD12 = 7U /**< Command Not Issued By Auto CMD12 Error. */
1263 } cy_en_sd_host_auto_cmd_status_t;
1264
1265 /** SD host error codes. */
1266 typedef enum
1267 {
1268 CY_SD_HOST_SUCCESS = 0U, /**< Successful. */
1269 CY_SD_HOST_ERROR = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 1U, /**< Non-specific error code. */
1270 CY_SD_HOST_ERROR_INVALID_PARAMETER = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 2U, /**< The provided parameter is not valid. */
1271 CY_SD_HOST_ERROR_OPERATION_IN_PROGRESS = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 3U, /**< A conflicting or requested operation is still in progress. */
1272 CY_SD_HOST_ERROR_UNINITIALIZED = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 4U, /**< The module (or part of it) was not initialized properly. */
1273 CY_SD_HOST_ERROR_TIMEOUT = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 5U, /**< A Time Out error occurred */
1274 CY_SD_HOST_OPERATION_INPROGRESS = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 6U, /**< The indicator for operation in progress. */
1275 CY_SD_HOST_ERROR_UNUSABLE_CARD = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 7U, /**< The card is unusable. */
1276 CY_SD_HOST_ERROR_DISCONNECTED = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 8U /**< The card is disconnected. */
1277 } cy_en_sd_host_status_t;
1278
1279 /** The widths of the data bus. */
1280 typedef enum
1281 {
1282 CY_SD_HOST_BUS_WIDTH_1_BIT = 0U, /**< The 1-bit mode data transfer width. */
1283 CY_SD_HOST_BUS_WIDTH_4_BIT = 1U, /**< The 4-bit mode data transfer width. */
1284 CY_SD_HOST_BUS_WIDTH_8_BIT = 2U /**< The 8-bit mode data transfer width. */
1285 } cy_en_sd_host_bus_width_t;
1286
1287 /** The bus speed modes. */
1288 typedef enum
1289 {
1290 CY_SD_HOST_BUS_SPEED_DEFAULT = 0U, /**< Default Speed mode: 3.3V signaling at 25 MHz SDClk. */
1291 CY_SD_HOST_BUS_SPEED_HIGHSPEED = 1U, /**< High Speed mode: 3.3V signaling at 50 MHz SDClk. */
1292 CY_SD_HOST_BUS_SPEED_SDR12_5 = 2U, /**< SDR12: UHS-I (1.8V signaling) at 25 MHz SDClk (12.5 MB/sec). */
1293 CY_SD_HOST_BUS_SPEED_SDR25 = 3U, /**< SDR25: UHS-I (1.8V signaling) at 50 MHz SDClk (25 MB/sec). */
1294 CY_SD_HOST_BUS_SPEED_SDR50 = 4U, /**< SDR50: UHS-I (1.8V signaling) at 100 MHz SDClk (50 MB/sec). */
1295 CY_SD_HOST_BUS_SPEED_EMMC_LEGACY = 5U, /**< Backwards Compatibility with legacy MMC card (26MB/sec max). */
1296 CY_SD_HOST_BUS_SPEED_EMMC_HIGHSPEED_SDR = 6U, /**< eMMC High speed SDR (52MB/sec max) */
1297 CY_SD_HOST_BUS_SPEED_DDR50 = 7U /**< DDR50: UHS-I (1.8V signaling) at 50 MHz SDClk (50 MB/sec). */
1298 } cy_en_sd_host_bus_speed_mode_t;
1299
1300 /** The SD bus voltage select. */
1301 typedef enum
1302 {
1303 CY_SD_HOST_IO_VOLT_3_3V = 0U, /**< 3.3V.*/
1304 CY_SD_HOST_IO_VOLT_1_8V = 1U /**< 1.8V. */
1305 } cy_en_sd_host_io_voltage_t;
1306
1307 /** Erase type. */
1308 typedef enum
1309 {
1310 CY_SD_HOST_ERASE_ERASE = 0U, /**< The ERASE operation.*/
1311 CY_SD_HOST_ERASE_DISCARD = 1U, /**< The DISCARD operation. */
1312 CY_SD_HOST_ERASE_FULE = 2U, /**< The Full User Area Logical Erase (FULE) operation. */
1313 CY_SD_HOST_ERASE_SECURE = 3U, /**< The secure purge according to
1314 * Secure Removal Type in EXT_CSD
1315 * on the erase groups identified by the
1316 * startAddr&endAddr parameters and
1317 * any copies of those erase groups.
1318 */
1319 CY_SD_HOST_ERASE_SECURE_TRIM_STEP_2 = 4U, /**< The secure purge operation on
1320 * the write blocks according to
1321 * Secure Removal Type in EXT_CSD
1322 * and copies of those write blocks
1323 * that were previously identified
1324 * using \ref Cy_SD_Host_Erase with
1325 * CY_SD_HOST_ERASE_SECURE_TRIM_STEP_1
1326 */
1327 CY_SD_HOST_ERASE_SECURE_TRIM_STEP_1 = 5U, /**< Mark the write blocks, indicated
1328 * by the startAddr&endAddr parameters,
1329 * for secure erase.
1330 */
1331 CY_SD_HOST_ERASE_TRIM = 6U /**< Trim the write blocks identified by
1332 * the startAddr&endAddr parameters. The controller
1333 * can perform the actual erase at convenient time.
1334 */
1335 } cy_en_sd_host_erase_type_t;
1336
1337 /** Card type. */
1338 typedef enum
1339 {
1340 CY_SD_HOST_SD = 0U, /**< The Secure Digital card (SD). */
1341 CY_SD_HOST_SDIO = 1U, /**< The CD Input Output card (SDIO). */
1342 CY_SD_HOST_EMMC = 2U, /**< The Embedded Multimedia card (eMMC). */
1343 CY_SD_HOST_COMBO = 3U, /**< The Combo card (SD + SDIO). */
1344 CY_SD_HOST_UNUSABLE = 4U, /**< The unusable or not supported. */
1345 CY_SD_HOST_NOT_EMMC = 5U /**< The card is not eMMC. */
1346 } cy_en_sd_host_card_type_t;
1347
1348 /** The card capacity type. */
1349 typedef enum
1350 {
1351 CY_SD_HOST_SDSC = 0U, /**< SDSC - Secure Digital Standard Capacity (up to 2 GB). */
1352 CY_SD_HOST_SDHC = 1U, /**< SDHC - Secure Digital High Capacity (up to 32 GB). */
1353 CY_SD_HOST_EMMC_LESS_2G = 0U, /**< The eMMC block addressing for less than 2GB. */
1354 CY_SD_HOST_EMMC_GREATER_2G = 1U, /**< The eMMC block addressing for greater than 2GB. */
1355 CY_SD_HOST_SDXC = 2U, /**< SDXC - Secure Digital Extended Capacity (up to 2 TB). */
1356 CY_SD_HOST_UNSUPPORTED = 4U /**< Not supported. */
1357 }cy_en_sd_host_card_capacity_t;
1358
1359 /** SDHC response types. */
1360 typedef enum
1361 {
1362 CY_SD_HOST_RESPONSE_NONE = 0U, /**< No Response. */
1363 CY_SD_HOST_RESPONSE_LEN_136 = 1U, /**< Response Length 136. */
1364 CY_SD_HOST_RESPONSE_LEN_48 = 2U, /**< Response Length 48. */
1365 CY_SD_HOST_RESPONSE_LEN_48B = 3U /**< Response Length 48. Check Busy after response. */
1366 }cy_en_sd_host_response_type_t;
1367
1368 /** The DMA type enum. */
1369 typedef enum
1370 {
1371 CY_SD_HOST_DMA_SDMA = 0U, /**< SDMA mode. */
1372 CY_SD_HOST_DMA_ADMA2 = 2U, /**< ADMA2 mode. */
1373 CY_SD_HOST_DMA_ADMA2_ADMA3 = 3U /**< ADMA2-ADMA3 mode. */
1374 }cy_en_sd_host_dma_type_t;
1375
1376 /** Write Protect type enum. */
1377 typedef enum
1378 {
1379 CY_SD_HOST_PERMANENT = 0U, /**< The permanent write protect. */
1380 CY_SD_HOST_ENABLE_TEMPORARY = 1U, /**< The temporary write protect. */
1381 CY_SD_HOST_DISABLE_TEMPORARY = 2U /**< Clear the temporary write protect. */
1382 } cy_en_sd_host_write_protect_t;
1383
1384 /** Card status in R1 response type enum. */
1385 typedef enum
1386 {
1387 CY_SD_HOST_AKE_SEQ_ERROR_R1_RESP = 3U, /**< Error in the sequence of the authentication process. */
1388 CY_SD_HOST_APP_CMD_R1_RESP = 5U, /**< The card will expect ACMD, or an indication that the command has been interpreted as ACMD. */
1389 CY_SD_HOST_FX_EVENT_R1_RESP = 6U, /**< Extension Functions may set this bit to get host to deal with events. */
1390 CY_SD_HOST_READY_FOR_DATA_R1_RESP = 8U, /**< Corresponds to buffer empty signaling on the bus. */
1391 CY_SD_HOST_CURRENT_STATE_0_R1_RESP = 9U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 0th bit. */
1392 CY_SD_HOST_CURRENT_STATE_1_R1_RESP = 10U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 1st bit. */
1393 CY_SD_HOST_CURRENT_STATE_2_R1_RESP = 11U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 2nd bit. */
1394 CY_SD_HOST_CURRENT_STATE_3_R1_RESP = 12U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 3rd bit. */
1395 CY_SD_HOST_ERASE_RESET_R1_RESP = 13U, /**< It indicates if an erase sequence was cleared before executing because an out of erase sequence command was received. */
1396 CY_SD_HOST_CARD_ECC_DISABLED_R1_RESP = 14U, /**< It indicates if the command has been executed without using the internal ECC. */
1397 CY_SD_HOST_WP_ERASE_SKIP_R1_RESP = 15U, /**< It is set when only partial address space was erased due to existing write protected blocks or the temporary or permanent write protected card was erased. */
1398 CY_SD_HOST_CSD_OVERWRITE_R1_RESP = 16U, /**< It indicates read only section of the CSD does not match the card content or there was an attempt to reverse the copy or permanent WP bits was made. */
1399 CY_SD_HOST_ERROR_R1_RESP = 19U, /**< A general or an unknown error occurred during the operation. */
1400 CY_SD_HOST_CC_ERROR_R1_RESP = 20U, /**< Internal card controller error. */
1401 CY_SD_HOST_CARD_ECC_FAILED_R1_RESP = 21U, /**< Card internal ECC was applied but failed to correct the data. */
1402 CY_SD_HOST_ILLEGAL_COMMAND_R1_RESP = 22U, /**< Command not legal for the card. */
1403 CY_SD_HOST_COM_CRC_ERROR_R1_RESP = 23U, /**< The CRC check of the previous command failed. */
1404 CY_SD_HOST_LOCK_UNLOCK_FAILED_R1_RESP = 24U, /**< Set when a sequence or password error has been detected in lock/unlock card command. */
1405 CY_SD_HOST_CARD_IS_LOCKED_R1_RESP = 25U, /**< When set, signals that the card is locked by the host. */
1406 CY_SD_HOST_WP_VIOLATION_R1_RESP = 26U, /**< Set when the host attempts to write to a protected block or to the temporary or permanent write protected card. */
1407 CY_SD_HOST_ERASE_PARAM_R1_RESP = 27U, /**< An invalid selection of write-blocks for erase occurred. */
1408 CY_SD_HOST_ERASE_SEQ_ERROR_R1_RESP = 28U, /**< An error in the sequence of erase commands occurred. */
1409 CY_SD_HOST_BLOCK_LEN_ERROR_R1_RESP = 29U, /**< The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. */
1410 CY_SD_HOST_ADDRESS_ERROR_R1_RESP = 30U, /**< A misaligned address which did not match the block length was used in the command. */
1411 CY_SD_HOST_OUT_OF_RANGE_R1_RESP = 31U, /**< The command's argument was out of the allowed range for this card. */
1412 } cy_en_sd_host_r1_response_t;
1413
1414 /** \} group_sd_host_enums */
1415
1416 /**
1417 * \addtogroup group_sd_host_data_structures
1418 * \{
1419 */
1420
1421 /******************************************************************************
1422 * Structures
1423 *****************************************************************************/
1424
1425 /** SD Host initialization configuration structure. */
1426 typedef struct
1427 {
1428 bool emmc; /**< Set to true of eMMC otherwise false. */
1429 cy_en_sd_host_dma_type_t dmaType; /**< Selects the DMA type to be used. */
1430 bool enableLedControl; /**< If true the SD clock controls one IO
1431 * used to indicate when the card
1432 * is being accessed.
1433 */
1434 } cy_stc_sd_host_init_config_t;
1435
1436 /** SD/eMMC card configuration structure. */
1437 typedef struct
1438 {
1439 bool lowVoltageSignaling; /**< If true, the host supports the 1.8V signaling. */
1440 cy_en_sd_host_bus_width_t busWidth; /**< The desired bus width. */
1441 cy_en_sd_host_card_type_t *cardType; /**< The card type. */
1442 uint32_t *rca; /**< The pointer to where to store the cards relative card address. */
1443 cy_en_sd_host_card_capacity_t *cardCapacity; /**< Stores the card capacity. */
1444 }cy_stc_sd_host_sd_card_config_t;
1445
1446 /** SD Host command configuration structure. */
1447 typedef struct
1448 {
1449 uint32_t commandIndex; /**< The index of the command. */
1450 uint32_t commandArgument; /**< The argument for the command. */
1451 bool enableCrcCheck; /**< Enables the CRC check on the response. */
1452 bool enableAutoResponseErrorCheck; /**< If true the hardware checks the response for errors. */
1453 cy_en_sd_host_response_type_t respType; /**< The response type. */
1454 bool enableIdxCheck; /**< Checks the index of the response. */
1455 bool dataPresent; /**< true: Data is present to
1456 * be transferred using the DAT line,
1457 * false: Commands use the CMD line only.
1458 */
1459 cy_en_sd_host_cmd_type_t cmdType; /**< The command type. */
1460 } cy_stc_sd_host_cmd_config_t;
1461
1462 /** The SD Host data transfer configuration structure. */
1463 typedef struct
1464 {
1465 uint32_t blockSize; /**< The size of the data block. */
1466 uint32_t numberOfBlock; /**< The number of blocks to send. */
1467 bool enableDma; /**< Enables DMA for the transaction. */
1468 cy_en_sd_host_auto_cmd_t autoCommand; /**< Selects which auto commands are used if any. */
1469 bool read; /**< true = Read from the card, false = Write to the card. */
1470 uint32_t* data; /**< The pointer to data to send/receive or
1471 * the pointer to the DMA descriptor.
1472 */
1473 uint32_t dataTimeout; /**< The timeout value for the transfer. */
1474 bool enableIntAtBlockGap; /**< Enables the interrupt generation at the block gap. */
1475 bool enReliableWrite; /**< For EMMC enables the reliable write. */
1476 }cy_stc_sd_host_data_config_t;
1477
1478 /** SD Host Write/Read structure. */
1479 typedef struct
1480 {
1481 uint32_t* data; /**< The pointer to data. */
1482 uint32_t address; /**< The address to Write/Read data on the card or eMMC. */
1483 uint32_t numberOfBlocks; /**< The number of blocks to Write/Read. */
1484 cy_en_sd_host_auto_cmd_t autoCommand; /**< Selects which auto commands are used if any. */
1485 uint32_t dataTimeout; /**< The timeout value for the transfer. */
1486 bool enReliableWrite; /**< For EMMC cards, enables the reliable write. */
1487 bool enableDma; /**< Enables DMA for the transaction. */
1488 } cy_stc_sd_host_write_read_config_t;
1489
1490 /** Context structure. */
1491 typedef struct
1492 {
1493 cy_en_sd_host_dma_type_t dmaType; /**< Defines the DMA type to be used. */
1494 cy_en_sd_host_card_capacity_t cardCapacity; /**< The standard card or the card with the high capacity. */
1495 uint32_t maxSectorNum; /**< The SD card maximum number of the sectors. */
1496 uint32_t RCA; /**< The relative card address. */
1497 cy_en_sd_host_card_type_t cardType; /**< The card type. */
1498 uint32_t csd[4]; /**< The Card-Specific Data register. */
1499 }cy_stc_sd_host_context_t;
1500
1501 /** \} group_sd_host_data_structures */
1502
1503
1504 /**
1505 * \addtogroup group_sd_host_high_level_functions
1506 * \{
1507 */
1508
1509 /******************************************************************************
1510 * Functions
1511 *******************************************************************************/
1512
1513 /* High level section */
1514
1515 cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base,
1516 cy_stc_sd_host_sd_card_config_t *config,
1517 cy_stc_sd_host_context_t *context);
1518 cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base,
1519 cy_stc_sd_host_write_read_config_t *config,
1520 cy_stc_sd_host_context_t const *context);
1521 cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base,
1522 cy_stc_sd_host_write_read_config_t *config,
1523 cy_stc_sd_host_context_t const *context);
1524 cy_en_sd_host_status_t Cy_SD_Host_Erase(SDHC_Type *base,
1525 uint32_t startAddr,
1526 uint32_t endAddr,
1527 cy_en_sd_host_erase_type_t eraseType,
1528 cy_stc_sd_host_context_t const *context);
1529
1530 /** \} group_sd_host_high_level_functions */
1531
1532 /**
1533 * \addtogroup group_sd_host_low_level_functions
1534 * \{
1535 */
1536
1537 cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base,
1538 const cy_stc_sd_host_init_config_t* config,
1539 cy_stc_sd_host_context_t *context);
1540 void Cy_SD_Host_DeInit(SDHC_Type *base);
1541 void Cy_SD_Host_Enable(SDHC_Type *base);
1542 void Cy_SD_Host_Disable(SDHC_Type *base);
1543 __STATIC_INLINE void Cy_SD_Host_EnableSdClk(SDHC_Type *base);
1544 __STATIC_INLINE void Cy_SD_Host_DisableSdClk(SDHC_Type *base);
1545 cy_en_sd_host_status_t Cy_SD_Host_SetSdClkDiv(SDHC_Type *base, uint16_t clkDiv);
1546 bool Cy_SD_Host_IsWpSet(SDHC_Type const *base);
1547 cy_en_sd_host_status_t Cy_SD_Host_SetHostBusWidth(SDHC_Type *base,
1548 cy_en_sd_host_bus_width_t width);
1549 cy_en_sd_host_status_t Cy_SD_Host_SetBusWidth(SDHC_Type *base,
1550 cy_en_sd_host_bus_width_t width,
1551 cy_stc_sd_host_context_t const *context);
1552 cy_en_sd_host_status_t Cy_SD_Host_SetHostSpeedMode(SDHC_Type *base,
1553 cy_en_sd_host_bus_speed_mode_t speedMode);
1554 cy_en_sd_host_status_t Cy_SD_Host_SetBusSpeedMode(SDHC_Type *base,
1555 cy_en_sd_host_bus_speed_mode_t speedMode,
1556 cy_stc_sd_host_context_t const *context);
1557 cy_en_sd_host_status_t Cy_SD_Host_SelBusVoltage(SDHC_Type *base,
1558 bool enable18VSignal,
1559 cy_stc_sd_host_context_t *context);
1560 void Cy_SD_Host_EnableCardVoltage(SDHC_Type *base);
1561 void Cy_SD_Host_DisableCardVoltage(SDHC_Type *base);
1562 cy_en_sd_host_status_t Cy_SD_Host_GetResponse(SDHC_Type const *base,
1563 uint32_t *responsePtr,
1564 bool largeResponse);
1565 cy_en_sd_host_status_t Cy_SD_Host_SendCommand(SDHC_Type *base,
1566 cy_stc_sd_host_cmd_config_t const *config);
1567 cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base,
1568 cy_stc_sd_host_data_config_t const *dataConfig);
1569 __STATIC_INLINE uint32_t Cy_SD_Host_BufferRead(SDHC_Type const *base);
1570 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_BufferWrite(SDHC_Type *base, uint32_t data);
1571 void Cy_SD_Host_ChangeIoVoltage(SDHC_Type *base, cy_en_sd_host_io_voltage_t ioVoltage);
1572 __STATIC_INLINE void Cy_SD_Host_StopAtBlockGap(SDHC_Type *base);
1573 __STATIC_INLINE void Cy_SD_Host_ContinueFromBlockGap(SDHC_Type *base);
1574 __STATIC_INLINE uint32_t Cy_SD_Host_GetAutoCmdErrStatus(SDHC_Type const *base);
1575 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAutoCmd23(SDHC_Type *base);
1576 __STATIC_INLINE void Cy_SD_Host_DisableAutoCmd23(SDHC_Type *base);
1577 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAsyncInterrupt(SDHC_Type *base);
1578 __STATIC_INLINE void Cy_SD_Host_DisableAsyncInterrupt(SDHC_Type *base);
1579 __STATIC_INLINE uint32_t Cy_SD_Host_GetAdmaErrorStatus(SDHC_Type const *base);
1580 __STATIC_INLINE void Cy_SD_Host_EMMC_Reset(SDHC_Type *base);
1581 cy_en_sd_host_status_t Cy_SD_Host_AbortTransfer(SDHC_Type *base,
1582 cy_stc_sd_host_context_t const *context);
1583 cy_en_sd_host_status_t Cy_SD_Host_WriteProtect(SDHC_Type *base,
1584 cy_en_sd_host_write_protect_t writeProtect,
1585 cy_stc_sd_host_context_t *context);
1586 uint32_t Cy_SD_Host_GetCardStatus(SDHC_Type *base, cy_stc_sd_host_context_t const *context);
1587 cy_en_sd_host_status_t Cy_SD_Host_GetSdStatus(SDHC_Type *base,
1588 uint32_t *sdStatus,
1589 cy_stc_sd_host_context_t const *context);
1590 uint32_t Cy_SD_Host_GetOcr(SDHC_Type *base, cy_stc_sd_host_context_t const *context);
1591 cy_en_sd_host_status_t Cy_SD_Host_GetCid(SDHC_Type *base, uint32_t *cid);
1592 cy_en_sd_host_status_t Cy_SD_Host_GetCsd(SDHC_Type *base,
1593 uint32_t *csd,
1594 cy_stc_sd_host_context_t *context);
1595 cy_en_sd_host_status_t Cy_SD_Host_GetExtCsd(SDHC_Type *base,
1596 uint32_t *extCsd,
1597 cy_stc_sd_host_context_t *context);
1598 uint32_t Cy_SD_Host_GetRca(SDHC_Type *base);
1599 cy_en_sd_host_status_t Cy_SD_Host_GetScr(SDHC_Type *base,
1600 uint32_t *scr,
1601 cy_stc_sd_host_context_t const *context);
1602 uint32_t Cy_SD_Host_GetPresentState(SDHC_Type const *base);
1603 bool Cy_SD_Host_IsCardConnected(SDHC_Type const *base);
1604 void Cy_SD_Host_SoftwareReset(SDHC_Type *base, cy_en_sd_host_reset_t reset);
1605 cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams,
1606 cy_en_syspm_callback_mode_t mode);
1607 cy_en_sd_host_status_t Cy_SD_Host_GetBlockCount(SDHC_Type *base,
1608 uint32_t *block_count,
1609 cy_stc_sd_host_context_t *context);
1610
1611
1612 /** \} group_sd_host_low_level_functions */
1613
1614 /**
1615 * \addtogroup group_sd_host_interrupt_functions
1616 * \{
1617 */
1618
1619 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptStatus(SDHC_Type const *base);
1620 __STATIC_INLINE void Cy_SD_Host_ClearNormalInterruptStatus(SDHC_Type *base, uint32_t status);
1621 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type *base, uint32_t interrupt);
1622 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptEnable(SDHC_Type const *base);
1623 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptMask(SDHC_Type *base, uint32_t interruptMask);
1624 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptMask(SDHC_Type const *base);
1625 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptStatus(SDHC_Type const *base);
1626 __STATIC_INLINE void Cy_SD_Host_ClearErrorInterruptStatus(SDHC_Type *base, uint32_t status);
1627 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type *base, uint32_t interrupt);
1628 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptEnable(SDHC_Type const *base);
1629 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptMask(SDHC_Type *base, uint32_t interruptMask);
1630 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptMask(SDHC_Type const *base);
1631
1632 /** \} group_sd_host_interrupt_functions */
1633
1634 /**
1635 * \addtogroup group_sd_host_low_level_functions
1636 * \{
1637 */
1638
1639
1640 /*******************************************************************************
1641 * Function Name: Cy_SD_Host_EnableSdClk
1642 ****************************************************************************//**
1643 *
1644 * Enables the SD clock (SD host drives the SDCLK line).
1645 *
1646 * \param *base
1647 * The SD host registers structure pointer.
1648 *
1649 *******************************************************************************/
Cy_SD_Host_EnableSdClk(SDHC_Type * base)1650 __STATIC_INLINE void Cy_SD_Host_EnableSdClk(SDHC_Type *base)
1651 {
1652 /* Check for NULL pointer */
1653 if (NULL != base)
1654 {
1655 SDHC_CORE_CLK_CTRL_R(base) = (uint16_t)((uint32_t)SDHC_CORE_CLK_CTRL_R(base) |
1656 SDHC_CORE_CLK_CTRL_R_SD_CLK_EN_Msk |
1657 SDHC_CORE_CLK_CTRL_R_PLL_ENABLE_Msk);
1658 }
1659 }
1660
1661
1662 /*******************************************************************************
1663 * Function Name: Cy_SD_Host_DisableSdClk
1664 ****************************************************************************//**
1665 *
1666 * Disables the SD clock (The SD Host doesn't drive the SDCLK line).
1667 *
1668 * \param *base
1669 * The SD host registers structure pointer.
1670 *
1671 *******************************************************************************/
Cy_SD_Host_DisableSdClk(SDHC_Type * base)1672 __STATIC_INLINE void Cy_SD_Host_DisableSdClk(SDHC_Type *base)
1673 {
1674 /* Check for NULL pointer */
1675 if (NULL != base)
1676 {
1677 /* Disable SD CLK */
1678 SDHC_CORE_CLK_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_CLK_CTRL_R(base),
1679 SDHC_CORE_CLK_CTRL_R_SD_CLK_EN, 0UL);
1680
1681 /* Wait for at least 3 card clock periods */
1682 Cy_SysLib_DelayUs(CY_SD_HOST_3_PERIODS_US);
1683
1684 /* Disable PLL */
1685 SDHC_CORE_CLK_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_CLK_CTRL_R(base),
1686 SDHC_CORE_CLK_CTRL_R_PLL_ENABLE, 0UL);
1687 }
1688 }
1689
1690
1691 /*******************************************************************************
1692 * Function Name: Cy_SD_Host_BufferRead
1693 ****************************************************************************//**
1694 *
1695 * Reads 32-bits of data from the read buffer.
1696 * Only use this function if not using SD block DMA to transfer data from buffer.
1697 *
1698 * \param *base
1699 * The SD host registers structure pointer.
1700 *
1701 * \return uint32_t
1702 * Data that is being read.
1703 *
1704 *******************************************************************************/
Cy_SD_Host_BufferRead(SDHC_Type const * base)1705 __STATIC_INLINE uint32_t Cy_SD_Host_BufferRead(SDHC_Type const *base)
1706 {
1707 /* Return the Buffer Data Port Register value */
1708 return SDHC_CORE_BUF_DATA_R(base);
1709 }
1710
1711
1712 /*******************************************************************************
1713 * Function Name: Cy_SD_Host_BufferWrite
1714 ****************************************************************************//**
1715 *
1716 * Writes 32-bits of data into the write buffer.
1717 * Only use this function if not using SD block DMA to transfer data to buffer.
1718 *
1719 * \param *base
1720 * The SD host registers structure pointer.
1721 *
1722 * \param data
1723 * Data to be written.
1724 *
1725 * \return \ref cy_en_sd_host_status_t
1726 *
1727 *******************************************************************************/
Cy_SD_Host_BufferWrite(SDHC_Type * base,uint32_t data)1728 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_BufferWrite(SDHC_Type *base, uint32_t data)
1729 {
1730 cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
1731
1732 /* Check for the NULL pointer */
1733 if (NULL != base)
1734 {
1735 SDHC_CORE_BUF_DATA_R(base) = data;
1736
1737 ret = CY_SD_HOST_SUCCESS;
1738 }
1739
1740 return ret;
1741 }
1742
1743
1744 /*******************************************************************************
1745 * Function Name: Cy_SD_Host_StopAtBlockGap
1746 ****************************************************************************//**
1747 *
1748 * Commands SD host to stop transmitting at the next block gap.
1749 *
1750 * \param *base
1751 * The SD host registers structure pointer.
1752 *
1753 *******************************************************************************/
Cy_SD_Host_StopAtBlockGap(SDHC_Type * base)1754 __STATIC_INLINE void Cy_SD_Host_StopAtBlockGap(SDHC_Type *base)
1755 {
1756 SDHC_CORE_BGAP_CTRL_R(base) = _CLR_SET_FLD8U(SDHC_CORE_BGAP_CTRL_R(base),
1757 SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ,
1758 1UL);
1759 }
1760
1761
1762 /*******************************************************************************
1763 * Function Name: Cy_SD_Host_ContinueFromBlockGap
1764 ****************************************************************************//**
1765 *
1766 * Commands SD host to continue transmitting after stopping at the block gap.
1767 *
1768 * \param *base
1769 * The SD host registers structure pointer.
1770 *
1771 *******************************************************************************/
Cy_SD_Host_ContinueFromBlockGap(SDHC_Type * base)1772 __STATIC_INLINE void Cy_SD_Host_ContinueFromBlockGap(SDHC_Type *base)
1773 {
1774 SDHC_CORE_BGAP_CTRL_R(base) = (uint8_t)(((uint32_t)SDHC_CORE_BGAP_CTRL_R(base) &
1775 ~SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ_Msk) | /* Clear the Stop At Block Gap Request bit. */
1776 SDHC_CORE_BGAP_CTRL_R_CONTINUE_REQ_Msk); /* Set the Continue Request bit. */
1777 }
1778
1779
1780 /*******************************************************************************
1781 * Function Name: Cy_SD_Host_GetAutoCmdErrStatus
1782 ****************************************************************************//**
1783 *
1784 * Gets the SD host error status of the auto command.
1785 *
1786 * \param *base
1787 * The SD host registers structure pointer.
1788 *
1789 * \return uint32_t
1790 * The bit mask of the Auto Command status.
1791 *
1792 *******************************************************************************/
Cy_SD_Host_GetAutoCmdErrStatus(SDHC_Type const * base)1793 __STATIC_INLINE uint32_t Cy_SD_Host_GetAutoCmdErrStatus(SDHC_Type const *base)
1794 {
1795 uint32_t ret;
1796
1797 ret = (uint32_t)SDHC_CORE_AUTO_CMD_STAT_R(base);
1798
1799 return ret;
1800 }
1801
1802
1803 /*******************************************************************************
1804 * Function Name: Cy_SD_Host_EnableAutoCmd23
1805 ****************************************************************************//**
1806 *
1807 * If the card supports AutoCmd23 call this function to enable it in the host.
1808 *
1809 * \param *base
1810 * The SD host registers structure pointer.
1811 *
1812 * \return \ref cy_en_sd_host_status_t.
1813 *
1814 *******************************************************************************/
Cy_SD_Host_EnableAutoCmd23(SDHC_Type * base)1815 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAutoCmd23(SDHC_Type *base)
1816 {
1817 cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
1818
1819 /* Check for the NULL pointer */
1820 if (NULL != base)
1821 {
1822 SDHC_CORE_XFER_MODE_R(base) = _CLR_SET_FLD16U(SDHC_CORE_XFER_MODE_R(base),
1823 SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE,
1824 2UL);
1825
1826 ret = CY_SD_HOST_SUCCESS;
1827 }
1828
1829 return ret;
1830 }
1831
1832
1833 /*******************************************************************************
1834 * Function Name: Cy_SD_Host_DisableAutoCmd23
1835 ****************************************************************************//**
1836 *
1837 * Removes support for AutoCmd23 if it was previously set.
1838 *
1839 * \param *base
1840 * The SD host registers structure pointer.
1841 *
1842 *******************************************************************************/
Cy_SD_Host_DisableAutoCmd23(SDHC_Type * base)1843 __STATIC_INLINE void Cy_SD_Host_DisableAutoCmd23(SDHC_Type *base)
1844 {
1845 SDHC_CORE_XFER_MODE_R(base) = _CLR_SET_FLD16U(SDHC_CORE_XFER_MODE_R(base),
1846 SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE,
1847 0UL);
1848 }
1849
1850
1851 /*******************************************************************************
1852 * Function Name: Cy_SD_Host_EnableAsyncInterrupt
1853 ****************************************************************************//**
1854 *
1855 * Enables the Asynchronous Interrupt for SDIO cards. Set this only
1856 * if the card supports this feature.
1857 *
1858 * \param *base
1859 * The SD host registers structure pointer.
1860 *
1861 * \return \ref cy_en_sd_host_status_t
1862 *
1863 *******************************************************************************/
Cy_SD_Host_EnableAsyncInterrupt(SDHC_Type * base)1864 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAsyncInterrupt(SDHC_Type *base)
1865 {
1866 cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
1867
1868 /* Check for the NULL pointer */
1869 if (NULL != base)
1870 {
1871 SDHC_CORE_HOST_CTRL2_R(base) = _CLR_SET_FLD16U(SDHC_CORE_HOST_CTRL2_R(base),
1872 SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE,
1873 1UL);
1874 }
1875
1876 return ret;
1877 }
1878
1879
1880
1881 /*******************************************************************************
1882 * Function Name: Cy_SD_Host_DisableAsyncInterrupt
1883 ****************************************************************************//**
1884 *
1885 * Removes the support for the Asynchronous Interrupt if it was previously set.
1886 *
1887 * \param *base
1888 * The SD host registers structure pointer.
1889 *
1890 *******************************************************************************/
Cy_SD_Host_DisableAsyncInterrupt(SDHC_Type * base)1891 __STATIC_INLINE void Cy_SD_Host_DisableAsyncInterrupt(SDHC_Type *base)
1892 {
1893 SDHC_CORE_HOST_CTRL2_R(base) = _CLR_SET_FLD16U(SDHC_CORE_HOST_CTRL2_R(base),
1894 SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE,
1895 0UL);
1896 }
1897
1898
1899 /*******************************************************************************
1900 * Function Name: Cy_SD_Host_GetAdmaErrorStatus
1901 ****************************************************************************//**
1902 *
1903 * Returns the ADMA Error Status register.
1904 *
1905 * \param *base
1906 * The SD host registers structure pointer.
1907 *
1908 * \return uint32_t
1909 * The bit mask of ADMA Error Status.
1910 *
1911 *******************************************************************************/
Cy_SD_Host_GetAdmaErrorStatus(SDHC_Type const * base)1912 __STATIC_INLINE uint32_t Cy_SD_Host_GetAdmaErrorStatus(SDHC_Type const *base)
1913 {
1914 uint32_t ret;
1915
1916 ret = (uint32_t)SDHC_CORE_ADMA_ERR_STAT_R(base);
1917
1918 return ret;
1919 }
1920
1921
1922 /*******************************************************************************
1923 * Function Name: Cy_SD_Host_EMMC_Reset
1924 ****************************************************************************//**
1925 *
1926 * Resets the eMMC card.
1927 *
1928 * \param *base
1929 * The SD host registers structure pointer.
1930 *
1931 *******************************************************************************/
Cy_SD_Host_EMMC_Reset(SDHC_Type * base)1932 __STATIC_INLINE void Cy_SD_Host_EMMC_Reset(SDHC_Type *base)
1933 {
1934 SDHC_CORE_EMMC_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_EMMC_CTRL_R(base),
1935 SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N,
1936 0UL);
1937
1938 /* Wait RST_n pulse width of 1 us */
1939 Cy_SysLib_DelayUs(CY_SD_HOST_EMMC_T_RSTW_US);
1940
1941 SDHC_CORE_EMMC_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_EMMC_CTRL_R(base),
1942 SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N,
1943 1UL);
1944
1945 /* Wait RST_n to Command time (74 cycles of clock signal required
1946 * before issuing CMD1 or CMD0 with argument 0xFFFFFFFA) - 200 us
1947 */
1948 Cy_SysLib_DelayUs(CY_SD_HOST_EMMC_T_RSCA_US);
1949 }
1950
1951 /** \} group_sd_host_low_level_functions */
1952
1953 /**
1954 * \addtogroup group_sd_host_interrupt_functions
1955 * \{
1956 */
1957
1958 /*******************************************************************************
1959 * Function Name: Cy_SD_Host_GetNormalInterruptStatus
1960 ****************************************************************************//**
1961 *
1962 * Returns the normal Int Status register.
1963 *
1964 * \param *base
1965 * The SD host registers structure pointer.
1966 *
1967 * \return uint32_t
1968 * The Bit mask of the normal Int Status.
1969 *
1970 *******************************************************************************/
Cy_SD_Host_GetNormalInterruptStatus(SDHC_Type const * base)1971 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptStatus(SDHC_Type const *base)
1972 {
1973 uint32_t ret;
1974
1975 ret = (uint32_t)SDHC_CORE_NORMAL_INT_STAT_R(base);
1976
1977 return ret;
1978 }
1979
1980
1981 /*******************************************************************************
1982 * Function Name: Cy_SD_Host_ClearNormalInterruptStatus
1983 ****************************************************************************//**
1984 *
1985 * Clears the selected SD host normal status.
1986 *
1987 * \param *base
1988 * The SD host registers structure pointer.
1989 *
1990 * \param status
1991 * The bitmask of statuses to clear.
1992 *
1993 *******************************************************************************/
Cy_SD_Host_ClearNormalInterruptStatus(SDHC_Type * base,uint32_t status)1994 __STATIC_INLINE void Cy_SD_Host_ClearNormalInterruptStatus(SDHC_Type *base, uint32_t status)
1995 {
1996 SDHC_CORE_NORMAL_INT_STAT_R(base) = (uint16_t)status;
1997 }
1998
1999
2000 /*******************************************************************************
2001 * Function Name: Cy_SD_Host_SetNormalInterruptEnable
2002 ****************************************************************************//**
2003 *
2004 * Sets the bit to be active in the Int status register.
2005 *
2006 * \param *base
2007 * The SD host registers structure pointer.
2008 *
2009 * \param interrupt
2010 * The Bit field of which normal interrupt status to enable.
2011 *
2012 *******************************************************************************/
Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type * base,uint32_t interrupt)2013 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type *base, uint32_t interrupt)
2014 {
2015 SDHC_CORE_NORMAL_INT_STAT_EN_R(base) = (uint16_t)interrupt;
2016 }
2017
2018
2019 /*******************************************************************************
2020 * Function Name: Cy_SD_Host_GetNormalInterruptEnable
2021 ****************************************************************************//**
2022 *
2023 * Returns which normal interrupts are enabled.
2024 *
2025 * \param *base
2026 * The SD host registers structure pointer.
2027 *
2028 * \return uint32_t
2029 * The Bit field of which normal interrupt statuses are enabled.
2030 *
2031 *******************************************************************************/
Cy_SD_Host_GetNormalInterruptEnable(SDHC_Type const * base)2032 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptEnable(SDHC_Type const *base)
2033 {
2034 uint32_t ret;
2035
2036 ret = (uint32_t)SDHC_CORE_NORMAL_INT_STAT_EN_R(base);
2037
2038 return ret;
2039 }
2040
2041
2042 /*******************************************************************************
2043 * Function Name: Cy_SD_Host_SetNormalInterruptMask
2044 ****************************************************************************//**
2045 *
2046 * Setting a bit in this register allows the enabled status to cause an interrupt.
2047 *
2048 * \param *base
2049 * The SD host registers structure pointer.
2050 *
2051 * \param interruptMask
2052 * The Bit field of which normal interrupts can cause an interrupt.
2053 *
2054 *******************************************************************************/
Cy_SD_Host_SetNormalInterruptMask(SDHC_Type * base,uint32_t interruptMask)2055 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptMask(SDHC_Type *base, uint32_t interruptMask)
2056 {
2057 SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base) = (uint16_t)interruptMask;
2058 }
2059
2060
2061 /*******************************************************************************
2062 * Function Name: Cy_SD_Host_GetNormalInterruptMask
2063 ****************************************************************************//**
2064 *
2065 * Returns which normal interrupts are masked to cause an interrupt.
2066 *
2067 * \param *base
2068 * The SD host registers structure pointer.
2069 *
2070 * \return uint32_t
2071 * The Bit field of which normal interrupts are masked to cause an interrupt.
2072 *
2073 *******************************************************************************/
Cy_SD_Host_GetNormalInterruptMask(SDHC_Type const * base)2074 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptMask(SDHC_Type const *base)
2075 {
2076 uint32_t ret;
2077
2078 ret = (uint32_t)SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base);
2079
2080 return ret;
2081 }
2082
2083
2084 /*******************************************************************************
2085 * Function Name: Cy_SD_Host_GetErrorInterruptStatus
2086 ****************************************************************************//**
2087 *
2088 * Returns the error Int Status register.
2089 *
2090 * \param *base
2091 * The SD host registers structure pointer.
2092 *
2093 * \return uint32_t
2094 * The bit mask of the error Int status.
2095 *
2096 *******************************************************************************/
Cy_SD_Host_GetErrorInterruptStatus(SDHC_Type const * base)2097 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptStatus(SDHC_Type const *base)
2098 {
2099 uint32_t ret;
2100
2101 ret = (uint32_t)SDHC_CORE_ERROR_INT_STAT_R(base);
2102
2103 return ret;
2104 }
2105
2106
2107 /*******************************************************************************
2108 * Function Name: Cy_SD_Host_ClearErrorInterruptStatus
2109 ****************************************************************************//**
2110 *
2111 * Clears the error interrupt status.
2112 *
2113 * \param *base
2114 * The SD host registers structure pointer.
2115 *
2116 * \param status
2117 * The bitmask of statuses to clear.
2118 *
2119 *******************************************************************************/
Cy_SD_Host_ClearErrorInterruptStatus(SDHC_Type * base,uint32_t status)2120 __STATIC_INLINE void Cy_SD_Host_ClearErrorInterruptStatus(SDHC_Type *base, uint32_t status)
2121 {
2122 SDHC_CORE_ERROR_INT_STAT_R(base) = (uint16_t)status;
2123 }
2124
2125
2126 /*******************************************************************************
2127 * Function Name: Cy_SD_Host_SetErrorInterruptEnable
2128 ****************************************************************************//**
2129 *
2130 * Setting a bit in this register allows for the bit to be active in
2131 * the Int status register.
2132 *
2133 * \param *base
2134 * The SD host registers structure pointer.
2135 *
2136 * \param interrupt
2137 * The Bit field of which error interrupt status to enable.
2138 *
2139 *******************************************************************************/
Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type * base,uint32_t interrupt)2140 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type *base, uint32_t interrupt)
2141 {
2142 SDHC_CORE_ERROR_INT_STAT_EN_R(base) = (uint16_t)interrupt;
2143 }
2144
2145
2146 /*******************************************************************************
2147 * Function Name: Cy_SD_Host_GetErrorInterruptEnable
2148 ****************************************************************************//**
2149 *
2150 * Returns which error interrupts are enabled.
2151 *
2152 * \param *base
2153 * The SD host registers structure pointer.
2154 *
2155 * \return uint32_t
2156 * The Bit field of which error interrupt statuses are enabled.
2157 *
2158 *******************************************************************************/
Cy_SD_Host_GetErrorInterruptEnable(SDHC_Type const * base)2159 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptEnable(SDHC_Type const *base)
2160 {
2161 uint32_t ret;
2162
2163 ret = (uint32_t)SDHC_CORE_ERROR_INT_STAT_EN_R(base);
2164
2165 return ret;
2166 }
2167
2168
2169 /*******************************************************************************
2170 * Function Name: Cy_SD_Host_SetErrorInterruptMask
2171 ****************************************************************************//**
2172 *
2173 * Setting a bit in this register allows the enabled status to cause an interrupt.
2174 *
2175 * \param *base
2176 * The SD host registers structure pointer.
2177 *
2178 * \param interruptMask
2179 * The Bit filed of which error interrupts can cause an interrupt.
2180 *
2181 *******************************************************************************/
Cy_SD_Host_SetErrorInterruptMask(SDHC_Type * base,uint32_t interruptMask)2182 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptMask(SDHC_Type *base, uint32_t interruptMask)
2183 {
2184 SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base) = (uint16_t)interruptMask;
2185 }
2186
2187
2188 /*******************************************************************************
2189 * Function Name: Cy_SD_Host_GetErrorInterruptMask
2190 ****************************************************************************//**
2191 *
2192 * Returns which error interrupts are masked to cause an interrupt.
2193 *
2194 * \param *base
2195 * The SD host registers structure pointer.
2196 *
2197 * \return uint32_t
2198 * The Bit field of which error interrupts are masked to cause an interrupt.
2199 *
2200 *******************************************************************************/
Cy_SD_Host_GetErrorInterruptMask(SDHC_Type const * base)2201 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptMask(SDHC_Type const *base)
2202 {
2203 uint32_t ret;
2204
2205 ret = (uint32_t)SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base);
2206
2207 return ret;
2208 }
2209
2210 /** \} group_sd_host_interrupt_functions */
2211
2212 #ifdef __cplusplus
2213 }
2214 #endif
2215
2216 /** \} group_sd_host */
2217
2218 #endif /* defined (CY_IP_MXSDHC) */
2219
2220 #endif /* CY_SD_HOST_PDL_H */
2221
2222
2223 /* [] END OF FILE */
2224
